Recommended Articles - December 2020
Specman and e-language abound in features, some of them are well known some others less known. In my last article, I focus on a less known feature which can be called as string templates
Recommended Articles - November 2020
AMIQ has published a new set of verification resources
. Cheatsheets for SystemVerilog and for SystemVerilog Assertions. When in need, every verification engineer now has a reference where to quickly search for basic information. SystemVerilog and SVA Cheatsheet
Manish, from Learn UVM Verification, continues his series on UVM RAL. This time he shows how to implement UVM RAL
Recommended Articles - October 2020
AMIQ has released a new UVC that facilitates register accesses. It is called Register Agent: Register Agent: A UVC for Register Access
Manish from Learn UVM Verification
explains why we need a UVM Register Abstraction Layer: Why UVM RAL is needed?
Cadence released a new feature that allows you to integrate Python code into e-language
. They now provide a nice example for visualizing the vr_ad register accesses in the form of a heatmap
. The Python code is OpenSource and you may use it in your e-Language project: Ouch that’s Hot! Register Access Heatmap
Recommended Articles - September 2020
Did you know that you can match strings using regular expressions from within SystemVerilog code? UVM implements a function called uvm_re_match. My colleague, Florin Oancea, explains how to use it and what you should pay attention at: How to Match Strings in SystemVerilog Using Regular Expressions
In the August edition
of the recommended articles I mentioned a challenge launched by Neil Johnson. The answers to this challenge are now posted by Dave Rich in his SystemVerilog Race Condition Challenge Responses
article. It is a good reference on what NOT to do when writing RTL or TB code.
Recently, I learned about an emerging and impressive AI System called GPT-3. This GPT-3 (Generative Pre-trained Transformer 3
) is an autoregressive language model that uses deep learning to produce human-like text. David Chalmers, an Australian philosopher, described GPT-3 as "one of the most interesting and important AI systems ever produced".
GPT-3 was used to write the following article. Can you distinguish it from a human being? A robot wrote this entire article. Are you scared yet, human?
But how is this GPT-3 system being verified? Yoav Hollander, already started to think about its verification: GPT-3 and verification
A LinkedIn post from Yousef B. Bedoustani, pointed out how same hardware design problem approached with two different mentalities can lead to very different solutions: RTL vs. Software Mentality in FPGA/ASIC Design; Latency From 161 to 2 Clock Cycle!
The FOSSI foundation announced that you can now produce your own physical chips. For free. In the Open
. The "open" part is guaranteed by the open source PDK (Process Design Kit) called Skywater PDK
. The "free" part is guaranteed by Google and efabless.
They are providing completely free of cost chip manufacturing runs: one in November this year, and multiple more in 2021. All open source chip designs qualify, no further strings attached!
Recommended Articles – August 2020
Ioana Cristea from Amiq shows how to achieve a non blocking communication between the SystemVerilog simulator and an external component, like Python: Non-Blocking Socket Communication in SystemVerilog Using DPI-C
Neil Johnson and Dave Rich have launched a challenge to the verification community. Discover and fix race conditions inside 10 SystemVerilog code snippets. Read more in SystemVerilog Race Condition Challenge
Recommended Articles - July 2020
Neil Johnson announced
he will take a step back and pass the leadership of SVUnit
project to Tudor Timisescu, aka Verification Gentleman
. SVUnit is a consistent and valuable contribution to the verification community and I am happy it is not lost. That's the OpenSource spirit at work!
Welcome back Manish! After four years of silence, LearnUvmVerification
comes back with: What is UVM RAL?
Chris Spear, from Mentor, is inviting us to explore what importing a SystemVerilog package means
The Fossi Foundation
promotes the opportunity of producing your own physical chips. For free. In the Open.
Recommended Articles - June 2020
SystemVerilog Multidimensional Arrays is a juicy topic for a blog post given they are feature reach. Here is a post that explains some of the features: SystemVerilog Multidimensional Arrays
A long-awaited feature comes into existence: adjusting verification environment behavior based on collected coverage items in real time at run time. Specman team facilitates this operation by means of coverage callbacks: Improving Tests Efficiency using Coverage Callback (part 2)
Recommended Articles - May 2020
Regressions can be an important resource consumer. Daniel Ciupitu, from AMIQ Consulting, provides a recipe for optimizing the disk usage when running regressions: How To Optimize Disk Space When Running Regressions
Elihai Maicas, from Intel, talks about RAL classes and how they affect performance. He offers a tip on how to deal with that. Read more in his Verification tip of the day
Chris Spear, from Mentor, reveals tips and tricks from his verification journey. The last one is about UVM Configuration DB
and how to optimize its performance.
Analyzing coverage during test run time and making decisions based on the coverage level. How does that sound? Specman introduced a coverage callback mechanism
for exactly that. This new feature touches similar area as our AMIQ CoverageLens application
. Have a look at both and thrust your verification power.
Recommended Articles - April 2020
Out of this DVCon presentation
Tudor got inspired and extended the solution of adding constraints into their own objects. Take a look at his new UVM journey: Favor Composition Over Inheritance - Even for Constraints
Elihai Maicas, from Intel, started a series of verification tips. Here is one of them on how to turn assertions off: Dynamically Turn-off a System-Verilog Assertion
Chris Spear, from Mentor, presents in an intuitive way what are parameterized classes
and static properties of the SystemVerilog classes
Recommended Articles - March 2020
In the CNN using HLS
post my colleague, Sergiu Duda, provides the long awaited code for the How to Implement a Convolutional Neural Network Using High Level Synthesis
HLS using C synthesis has brought FPGA implementation of computational intensive tasks into mainstream. Hardware for Deep Learning: Know Your Options
article proposes a new solution, called LeFlow, where the High Level Synthesis is done directly from the Python code. LeFlow
aims to realize a seamless transition between training on a GPU cluster and the deployment on an FPGA.
Recommended Articles - February 2020
After a long pause, Tudor Timisescu wrote a new post about compilation time of SystemVerilog code and how it is impacted by the code aggregation in SystemVerilog packages. Under certain conditions, changing a single file might result in recompilation of the whole code. Find out why in Bigger Is Not Always Better: Builds Are Faster with Smaller Packages
SystemVerilog includes a feature called variable shadowing. Usually, this feature is considered a bit dangerous and care must be taken, but Cristian from CFSVision has found a benefit in using it. Read about Cristian's findings in SystemVerilog: How To Hide Your Fields So That Anyone Can Find Them
Recommended Articles - January 2020
A bit of history on how DMA (Direct Memory Access) works. Despite being 6 years old, it worth the lecture: An overview of direct memory access
What is open-source hardware? If you had the same question, you might be interested in this article: Open source hardware risks
. Also, the article brought to my attention the following projects: OpenTitan
, Root of Trust in cryptography, Chiplet technology
, IBEX RISC-V core
, Ariane Risc-V CPU
In contrast to the above article on Open Source Hardware, a colleague of mine indicated an article by Paul McLellan (Cadence) describing a different view on the open-source paradigm: Open source in 2020
. Paul reveals a webpage which seems to be the first in line when it comes to critique on open source concept. It is called The Cathedral and the Bizarre
, a parody name in response to the book The Cathedral and the Bazaar
written by Eric S. Raymond in 1998, who laid the foundation for open source movement.
Recommended Articles - December 2019
In early 2018, AMIQ released a new library called FC4SC (Functional Coverage for SystemC). The community responded in a positive manner and started to evaluate it and asked for improvements. Late this year, the library has been donated to Accellera in order to fill the functional coverage gap from the SystemC world. More on the reasoning behind the library and its future in this article: AMIQ Consulting Contributes C++ Coverage Library to Accellera
Adam Rose, from Verilab, wrote a paper
in the form of enhancement proposals for the SystemVerilog language standard. He looked at Python and C++ and tried to borough concepts and apply them to SystemVerilog. In this new SystemVerilog language quest (anonymous classes, introspection, decoration), he described how code constructs like uvm_macros, uvm_factory, constraints and functions would morph into a different kind of code constructs and not only. I think the final paragraph summarizes the goal of the paper:
In many ways, these enhancements simply bring SystemVerilog up to date with recent
developments in programming languages. By using them, Verification engineers will be able
to enhance their productivity by writing more concise, modular and maintainable code.
Recommended Articles - November 2019
A while ago, the Specman team announced that you may now take advantage of Python in the e-language world
. Lately, the same team has described one of the possible applications which makes use of this Python support. For example you can now analyze your coverage results using Python
. Can you imagine another kind of application? Please share your thoughts on this.
Recommended Articles - September 2019
Did you ever had the need to programmatically dump the values of signals from a simulation? SystemVerilog offers such a dumping capability by means of system tasks. The signal values are dumped into a vcd (value change dump) file. The vcd files can later be read by a waveform viewer and examine signals' behavior. Read about those tasks in here
Yoav Hollander, the inventor of e-language, announced on his Foretellix Blog, that a new verification language has just emerged. It is called M-SDL, the autonomous vehicles verification language. M-SDL stands for Measurable Scenario Description Language. It is intended to be an open language and aims to make Autonomous Vehicles safer and more reliable. Read more in here
UVM and PSS are not competing but they are complementing each other. Tom Fitzpatrick shows some concrete examples on how this is achieved. Read more in Portable stimulus and UVM
Recommended Articles – August 2019
Dan Gisselquist presents some statistics on how much time various formal proofs have taken him to complete. He also gives some advice on what to look for when trying to keep your proof times short: Just how long does a formal proof take to finish?
Recommended Articles - July 2019
When working with pointers, the pointer arithmetic is quite important. Colin Walls, from Mentor, wrote a nice, short article on why and when to store addresses in pointer variables and when to store them in a regular variable. Read more in here: Using an unsigned integer to store a pointer in C
Recommended Articles - May 2019
Cristian Bob posted a new article showing how to connect Python to e-language: How to Connect e-Language with Python
Dan Gisselquist has written an interesting tutorial regarding formal methods: SVA and FormalTools: An Introduction to Formal Methods
A long-awaited feature for e-language has now been released by the Specman Team: spawning multiple processes using loops. You can read more about it in the second part of Concurrent Actions in Specman
One of our readers, Kaushal Modi, has got our attention
with a new language called Nim. As the Nim website
indicates "Nim is a statically typed compiled systems programming language with a design that focuses on efficiency, expressiveness, and elegance
". Kaushal pointed out that instead of using C language to connect to SystemVerilog via DPI-C, Nim could replace C language or it could be a proxy with other languages. Here is a presentation on Nim, DPI-C and SystemVerilog
Yoav Hollander(Foretellix) posted ASAM, DeepMind, Tesla and more
, an article that touches few interesting topics for autonomous vehicles verification. As an appetizer you can have a look at DeepMind
's paper "Rigorous Agent Evaluation: an adversarial approach to uncover catastrophic failures
" that presents a method for bug hunting and risk estimation of Machine-Learning-based systems.
Recommended Articles - March 2019
Cristian Bob (AMIQ) leveraged the power of Python into a SystemVerilog testbench using a client-server architecture. The post How to Connect SystemVerilog with Python
is a must-read if you use or plan to use Python along with SystemVerilog. It is natural to see Python infiltrating the verification world given it's popularity (see TIOBE index
) and its applications spectrum.
Mattew Ballance(Mentor, A Siemens Business) wrote a short guide on how to think about PSS when it comes to your own application: Selecting a Portable Stimulus Application Focal Point
I'm a long time user of e-language so I regularly read TeamSpecman's blog. This month they wrote about Concurrent Actions in Specman
. The post describes first of
and all of
constructs, which resemble the SystemVerilog fork join/join_any
Given that functional verification is about 90% software and 10% "hardware", I recommend this website
. RefactoringGuru presents in a very friendly way how/when to refactor your code
and design pattern concepts and recipes
that can be leveraged in verification engineer's day to day work.
Recommended Articles - February 2019
It looks like February is a short month and probably people were focused more on preparing for the DvCon US 2019 conference. Let's meet again in March with new and interesting technical content from our domain.
Recommended Articles - January 2019
New entry on our list.
Recently, I found a new source of interesting papers related to UVM and Verification. It is the Rochester Institute of Technology (RIT) Scholar Works
. RIT is a tech University from New-York, USA. Of particular interest are the theses papers published on their website
. Here are some papers which tackle various topics:
Interfacing SystemVerilog with C language is a common thing nowadays. Mapping the data types between the two languages might become troublesome, thus the need for this article: How to Call C-functions from SystemVerilog Using DPI-C
Dave Rich, is one of the industry experts in SystemVerilog and UVM. He started a series of posts which may help newbies and experts alike in absorbing knowledge required by the verification activity. In one of the articles, he talks about SystemVerilog classes for UVM verification
and in a second article he's presenting some of the usual design patterns in SystemVerilog OOP
Portable Stimulus can be used to create better virtual sequences. This is the story which Matthew Ballance presents in this article from Verification Academy
Cadence has published new videos which can be used as a training source for learning SystemVerilog
. Here is the first video
from Brian Dickinson.
Yoav Hollander, the creator of e-language, is leading the way in getting safer AVs (autonomous vehicles). It is a brand new territory where innovation and challenges are day to day activities. In his last January post
, he's challenging the idea that Monte Carlo simulations (which use the expected distribution) are safe to use in AV verification.
Recommended Articles - December 2018
Sergiu Duda from AMIQ has put a lot of effort into creating a high quality article on the non-trivial topics of High Level Synthesis and Deep Learning. The later, is not found in the everyday terminology of a verification engineer. Deep learning is just a flavour of a bigger part called Machine Learning which in its turn is part of the bigger, Artificial Intelligence.
I do think you will get more meaning out of this topic after spending your time on reading his article: How to Implement a Convolutional Neural Network Using High Level Synthesis
Recommended Articles - November 2018
New data arrived from the 2018 Wilson Research Group Functional Verification Study. This research is done every two years and it shows trends in our functional verification domain. If you are interested in the data you can read the set of articles that will follow on verification horizons. Here are the first ones: Prologue
, Part 1
and Part 2
Cristian continues his series on SystemC tutorial. This time he is talking about module hierarchy and connectivity
Recommended Articles - October 2018
Cristian from CFSVision wrote a short tutorial on how to work with SystemVerilog queues
Cadence published a new article in the series regarding SystemVerilog code optimizations. This time it tackles the subject of creating and managing dynamic objects
AnySilicon published an article aiming to describe the stages of ASIC production
. The big picture always helps to a better understanding of our domain.
Recommended Articles - September 2018
In case of e-language it is the aspect oriented-nature of the language itself that helps cutting down the compile and simulation rerun time. You can read more about dynamic load or just-in-time patching: Adding a Patch Just in Time!
I always try to find ways of shortening the time it takes to wait for various actions like: compilation, simulation, debug, analyze. Such a time saving feature is e-language's patching/extension capability due to its aspect oriented nature of the language. But Cadence made it to the next level, adding a patch on top of an existing compilation or restarting a previous simulation from a specific timepoint and loading a new piece of code on top of the previous simulation. Read more in:
Verification Academy has published a new version of the UVM 1800.2 Cookbook
. You need to login if you want to download it.
Recommended Articles - August 2018
In his article about how to avoid FIFO overflows, Stefan promised a second solution. Here is part II of the article
presenting the solution which makes use of uvm constructs.
Neil from AgileSOC continues to simplify the SVAUnit framework. He makes use of his new mocking framework in order to decouple the driver from the sequencer. In this way he is able to UnitTest the UVM drivers without the sequencer
. Then he applies the same concept on the sequences
. Another idea from his side is make use of the popular wavedrom application in order to generate test stimuli for UnitTesting
. I personally like the idea of transforming waveforms into a piece of code.
Recommended Articles - July 2018
AMIQ Education Program saga continues.... This years' summer school received more attention from the students according to Stefan's feedback: Digital Circuits Simulation and Verification Summer School
FIFOs are encountered in many digital designs and the verification of such designs comes with specific challenges, one of them being to protect the FIFOs against overflow. You can read more about it in: How To Protect FIFOs Against Overflow
post. An alternative implementation will be given in a follow-up post.
AMIQ and Cadence have exhibited at DAC 2018 on the support they provide for the new Portable Stimulus Standard (PSS): AMIQ and Cadence demonstrate Accellera PSS v1.0 interoperability
Neil Johnson has created a mocking framework for the SVUnit called SVMock. You can read more about it here: SVMock Version 0.1
Recommended Articles - June 2018
We present to you the SystemVerilog and VHDL Grammars in HTML format
. The grammars represent the BNF (Backus-Naur Form) notation in an HTML format, with hyperlinks, anchors and tooltips. You can also download them from the GitHub repository
John Neil, from AgileSOC, continues his reflection on how verification engineers should think about their testbench code: AgileSOC: Balancing Verification Development With Delivery
Cadence continues its series of SystemVerilog code optimization. They are provided as guidelines, which if thought before writing a single line of code, can help with simulation performance: Part II
, Part III
Here is a new way of controlling e-language generator. It is done by the help of the so called Range Generated Fields: Empowering Generation - Range Generated Fields (RGF)
In June the verification community had an opportunity to share ideas and solutions regarding verification, by means of Verification Futures 2018 conference. If you missed it, you can check out the presentation slides and videos over here: Verification Futures 2018
Recommended Articles - May 2018
Here is an interesting article discussing if any FPGA implementation contains an internal tri-state bus or not: FPGA internal tri-state buses
I'm not a fan of long articles, but the subject of the following ones is of real interest for verification engineers. It is a transcript of a discussion between representatives of major EDA companies about EDA tools and their option of going to the cloud. Tools and the future of those tools might influence how we do verification in the future. You can read their discussion in a series of three articles from Brian Bailey-SemiEngineering: EDA in the cloud Part1
A short introduction to the AMBA bus
and the AXI protocol
can be read on the AnySilicon website.
Every experienced verification engineer has been at least once through the scenario described by Mark Glasser in his last article: Debugging madness
. The way we can deal with these kind of "brain stalls" is diverse. It might also help if we understand how the brain works and how learning process works. I strongly suggest to follow up a course about "Learning How to Learn
" from Coursera.
Neil Johnson steps out of the verification circle and uses his critical thinking to address the high level picture about Verification. He also tries to connect the dots through the lens of his past experiences in verification. Verification Planning with shared objectives
is considered, followed by metrics for design maturity
and then finding a cure for what he calls "coverage hangover
Recommended Articles - March 2018
Team Specman casts a new light on how to make the verification environment sensitive to reset. You can read about that in Temporals, Reset, and Test Phases
Cadence has compiled some short guidelines which can optimize your SystemVerilog code. Take a look at them and check which one is already on your list and which is not. App Note Spotlight: Streamline Your SystemVerilog Code, Part I
Recommended Articles - April 2018
This month, Neil Johnson (AgileSOC) has challenged the verification community
in an attempt to define a scope for the new Portable Stimulus Standard (PSS) and a place among the other existing verification techniques. He presents his view in a series of three articles. One of the articles
presents each verification technique and its scope. In a following article Neil presents how a verification engineer could determine when to use or not any of the verification techniques
Recommended Articles - February 2018
Ben Cohen, a leading expert on SystemVerilog Assertions (SVA), wrote an article about Concurrent Assertions and their limitations when it comes to using delays inside SVAs. He also shows how to replace complex assertions with tasks. In the end, he points it out nicely: "implementing an assertion with tasks is acceptable; SVA is just a shorter notation that adapts well for most cases, but not all cases." Read it all in SVA Alternative for Complex Assertions
Teo from AMIQ, implemented another nice feature which brings the coverage concept from HVL (Hardware Verification Languages) into C++ language. It already gained a fan. Read it all here: C++ Implementation of Functional Coverage for SystemC
If you were ever curious what is new in the SystemVerilog IEEE Std.1800-2017 standard compared to the one from 2012, then this is the article to read from Verilab: Thoughts on the updated standard, by Principal Consultant Jonathan Bromley
Recommended Articles - January 2018
Jason, from VerilogPro, dives into the details of generate constructs from verilog and how they can be used to build a configurable RTL: Verilog Generate, Configurable RTL Designs
Horia has come with some alternative implementations for bitwise coverage in SystemVerilog. Here you can see his implementations: How To: Alternative ways to implement bitwise coverage
Cadence has shared some nice macro code for its Specman users. The macros are helpful when dealing with coverage (minimum and maximum of a type). Read the full details
Recommended Articles – December 2017
CFSVision continues the SystemC tutorial with an indepth explanation of the signal channels: Learning SystemC: Learning SystemC: #005 Signal Channels
PSS starts to be more and more present on verification blogs. Mike Bartley from T&VS and Sharon Rosenberg from Cadence co-edited Portable Stimulus Specification (PSS) and the Reuse Revolution
Giselquist Technologies presents how to build a simple logic PLL
. This article helps you understand how logic PLLs work, which is important if you need to verify clock generators or clock recovery blocks.
AMIQ released a second version of the Open Source CoverageLens application. The new release extends the UCIS database inspection capabilities, as described in CoverageLens 2.0 Release
Recommended Articles - November 2017
TeamSpecman extends e-Language with annotations: Adding Annotations in Your e Code
, which are similar to Java annotations
SemiEngineering shows how PSS helps one to reuse tests from IP-level to SoC-level
Horia from Amiq demonstrates how to avoid parameter creep
in SystemVerilog by using packed struct
. This comes as a continuation of Stefan's previous article
Yoav Hollander keeps exploring the hazy AV verification territory:
Verifying how AVs behave during accidents
Recommended Articles – October 2017
Cristian from CFSVision continues the SystemC series
with two new tutorials addressing Time, Events and Processes
and Mutex, Semaphores and FIFOs
Stefan from Amiq shows how to create a custom sequencer arbitration policy
Recommended Articles - September 2017
CFSVision continues the SystemC tutorial with an indepth explanation of the sc_module: Learning SystemC: #002 Module – sc_module
FPGA4Student explains how to implement a car parking system in VHDL.
Working both with SystemC and SystemVerilog is not always an easy task. Teo from AMIQ facilitates understanding of data structures mirroring between SystemVerilog and SystemC: How to Align SystemVerilog-to-SystemC TLM Transactions Definitions
Recommended Articles - August 2017
New entry on our list
FPGA4Student is a website dedicated to provide a lot of source code for various FPGA needs. It's a good resource for learning how to code in Verilog or VHDL. Here is a comparison between Verilog and VHDL: Explain by Examples
Jason Yu from VerilogPro is set to compare implementation of arrays from Verilog versus SystemVerilog. He starts with the Verilog Arrays Plain and Simple
Cristian Slav from CFSVision continues his SystemC Learning. After a basic introduction and installation
, he moves to the Data Types of SystemC
SystemC language is lacking support for functional coverage. But when SystemC runs together with SystemVerilog, that inconvenience can be alleviated. Here is a tutorial on how to harness the power of SystemVerilog functional coverage constructs in a SystemC model: AMIQ Blog: How to Export Functional Coverage from SystemC to SystemVerilog
You can find the latest news about AMIQ Education Program in this new article by Stefan: Amiq Education Program Updates Summer 2017
Verification Summer School is a great way for students to learn about how we verify Digital Circuits, IC and SoCs. This year, we decided to open the source code of the school labs held by AMIQ. You can read more about it here: AMIQ Blog: Open Source Summer School Labs
This is an old article by Jonathan Rentzsch (IBM, 2005) that's worth reading. It tells the story of how data alignment and memory granularity influences the performance of a CPU: Data alignment: Straighten up and fly right
Recommended Articles - July 2017
Tudor (Verification Gentleman) continues his series of articles on unit testing with a case study on Testing SVA Properties and Sequences
Ben Cohen (SystemVerilog.us
) goes into details on how tasks and threads are used inside System Verilog Assertions. The Understanding the SVA Engine + Simple alternate solutions
article also includes an SVA example that is easier to write using tasks.
Dan Gisselquist (Gisselquist Technology
) shows How to Debug a DSP algorithm
by using Octave. Amiq has also been using Octave inside UVM test-benches
to offload the work on complex mathematical computations.
Teo (Amiq) writes about one of our in-house tools that help with code coverage analysis: Coverage Lens
. You can download the tool from GitHub
Recommended Articles - June 2017
UVM provides callbacks mechanism that allows one to expand code's functionality. Munjal explains advanced usage of callbacks in UVM
You might remember, from the highlights of DVCon US 2017 conference
, that we recommended a paper about constrained random and dynamic seed manipulation ("Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation"). The presenter, Eldon Nelson, working on Intel, owns a blog called Ten Thousand Failures
and he made his paper publicly available in his latest June post. Check all the details of his solution over here: IMPROVING CONSTRAINED RANDOM TESTING - SECOND PLACE PAPER AT DVCON 2017
Mark Glasser from Verification Land, has written an interesting article, Fun with Type Handles,
about working with type handles in SystemVerilog. It is more or less a design pattern, used also inside UVM's code. The pattern helps out when dealing with SystemVerilog types at run-time.
Cristian from CFSVision, started a series about how to handle reset in UVM. He takes his first part
of the series and expands it with an explanation of the race conditions in relation to the order of reset threads: SystemVerilog: How To Handle Reset In UVM (part 2)
Horia from AMIQ, continues the series of posts about packing/unpacking in SystemVerilog. This month the focus is placed on the unpacking mechanism from SystemVerilog:How to Unpack Data Using the SystemVerilog Streaming Operators (>>, <<)
. I consider it to be one of the best tutorials about packing and unpacking.
Recommended Articles - May 2017
Yet another way of connecting the testbench components to the interface containing the signals. Learn more about accessor classes and parametrization in the article How To Reduce the Number of VIP Instances using Accessor Classes
We have a new entry on our radar
. Mark Glasser displays his view of an SVlogical way of writing code. You can see it as tips&tricks
for writing SystemVerilog code. He wrote another article about assumptions in verification
. It can be very difficult to deal with assumptions. They might be hidden behind a piece of code or behind a verification plan. Take your time to read the articles and don't make any assumptions.
Did you ever wondered what's the difference between Verilog reg, Verilog wire and SystemVerilog logic? Jason Yu from VerilogPro takes this question and brings an eloquent answer to it:Verilog reg, Verilog wire, SystemVerilog logic. What’s the difference?
Here is a graphical representation of the SystemVerilog packing operation using streaming operators. I've been waiting for it since long time ago and I think the same goes for all of you. Check out Horia's new article: How to Pack Data Using SystemVerilog Streaming Operators (>>, <<)
Recommended Articles - April 2017
There are multiple ways of connecting a SystemVerilog interface instance to a virtual interface inside the verification environment. Cristian, described two ways of doing just that. One good old simple way when having just one interface instance and another one for multiple instances.
CFSVision: UVM: How to Pass a Virtual Interface from Testbentch to Environment
Recommended Articles - March 2017
Using SystemVerilog along UVM methodology can be a difficult road for a newbie. Mentor together with Sandeep Nasa and Shankar Arora from Logic Fruit Technologies
, have compiled a list of UVM tips&tricks that help you avoid some of the language traps and might improve performance. Read more on UVM Tips and Tricks
Cadence has added static
members in the e-language, so from now on you can share configuration, coverage or fields among all instances of a struct/unit. Take a look at this new feature in Static members in e
Communication within an UVM environment is mainly done using ports (analysis, TLM, etc.). A complex hierarchy of port connections slows down the debug...well, not for Munjal which describes a way to speed-up the debug: How to find UVM port connections between components in the testbench
This year DVCon US enchanted us with few innovative approaches on verification challenges. See more in AMIQ's Highlights of DVCon US 2017
You take a 3rd year student, a mentor and an idea and stir (not shake) them. Read about the result on AMIQ's blog: Mentoring Young Talent Through Hands-on Applications
. This is part of the AMIQ Education Program
Recommended Articles - February 2017
is fun. Solving sudoku using SystemVerilog is both fun and instructive. In a 2015 article
, Keisuke Shimizu from ClueLogic, provided a SystemVerilog solution for solving sudoku. In the 2017 version he provides a different solution that makes use of "unique
" SystemVerilog keyword. Read all about it here: Hidden Gems of SystemVerilog – 4. Solving Sudoku with Uniqueness Constraints
a new version of the e
-Language standard: IEEE 1647-2016
. If you are into history you can download the older IEEE-1647 2011
Munjal presents us How to disable triggering of an UVM event
An interesting topic was addressed recently by Bryan Murdock. He talks about programming languages and design patterns. In particular, he compares SystemVerilog language + UVM methodology and Python. The take away idea is that UVM implements ~ 11 design patterns while Python in its nature, intrinsically, provides out of the box 7 of these 11. Thus, if you were to implement UVM using Python, you would be left with only 4 design patterns to implement, all the others are there already, in the language itself. Here are the full details: SystemVerilog and Python
AMIQ announces the release of the SVAUnit 3.2
Recommended Articles - January 2017
SystemVerilog standard provides structure
data types. Jason Yu, from Intel, has tried to use them for RTL design and he shared his experience via this VerilogPro article: Using SystemVerilog Structures and Unions in a Design
AMIQ Consulting created an UVM/SystemVerilog application that exports existing UVM register models to an IP-XACT file in order to ease IP-XACT adoption. The application is available for free under the Apache License 2. See more at UVM Register Model to IP-XACT Application
Recommended Articles - December 2016
Often, it happens that the information about a D
est (DUT) or about its verification is being organized in the form of a table like structure (configurations, registers, operation modes, traffic types, etc.). Imagine if you could automatically create bits of code from an Excel table. How awesome is that! E-language is now able to do just that. The power of the in_table
construct is now doubled if combined with the e-language macros table_row
and table from file with
. Check out the details in Cadence's article: Creating Code from Tables
AMIQ wrote a series of articles with the goal of educating graduates/engineers about WHAT does it mean to be a Verification Engineer
and HOW you can become a Verification Engineer
. Daniel Ciupitu, from AMIQ, continued the series answering the WHY
question: AMIQ Blog: To be or not to be a Verification Engineer
AMIQ is an active contributor to design and verification conferences. You can now access AMIQ's papers and presentations timeline on the Papers web-page
Since holiday season is close-by, I wish you Merry Christmas and all the best during 2017!
Recommended Articles - November 2016
Every design or verification engineer needed at some point in time a basic compile/run script. Go2UVM presents a basic compile/run script that supports all 4 major simulators (Incisive, VCS, QuestaSim and RivieraPro):
Go2UVM: Generic Makefile for UVM simulations
Go2UVM shows the basics of using variable delays in SystemVerilog Assertions:
GO2UVM: Handling variable delays in SystemVerilog Assertions
Manish Singhal opens a new topic: emulation. In this post he introduces the reader to emulation and explains the basic difference between emulation, simulation and prototyping:
LearnUVMVerification: What is Emulation?
Munjal explores a different way of creating stimulus using UVM's uvm_random_stimulus
Munjal: UVM Random Stimulus Generator
Every activity domain makes use of patterns and functional verification is no exception. AMIQ engaged into a quest of discovering and revealing functional verification patterns. Here is the 4'th entry on our list of Functional Verification Patterns
AMIQ Blog: Functional Coverage Patterns: The Counter
AMIQ is dedicated to introduction of functional verification as a study subject in the Romanian technical colleges. Here is another step forward:
AMIQ Blog: Pre-Silicon Verification Course at Politehnica University of Timișoara
AMIQ was present at the DVCon Europe 2016 in Germany, Munich. Ionuț Ciocîrlan presents the highlights of this year's conference. Technical curating is not easy, but Ionuț makes it feel simple and pleasant to read:
AMIQ Blog: Highlights of DVCon Europe 2016
Recommended Articles - October 2016
New entry on our list
is a nice resource for FPGA/VHDL enthusiasts. Claudio Avi Cham, the owner of the website, shows how to implement an arbiter in VHDL:
FPGASite: VHDL Arbiter Part 1
, Part 2
, Part 3
What does a Functional Verification Engineer (FVE) do and how can you become an FVE? Stefan Birman, Managing Partner at AMIQ Consulting, answers this question, as close as possible to the reality of the Semiconductor Industry:
AMIQ Blog: Pre-Silicon Digital Functional Verification Engineer – The Job Description
The e-language users can download and use the I2C eVC (released by AMIQ as an Open Source eVC):
AMIQ Blog: amiq_i2c – ‘e’ Verification Component for I2C Protocol
Rich Edelman from Mentor presents in Debugging My UVM Factory and UVM Config
how to improve the UVM Factory code in order to ease debug. He tells the story of a bug that was not easy to catch unless he instrumented the UVM code. Last week I also got a live preview of his article when I attended the presentation (5.2) of his colleague, Dirk Hansen
at DVCon Europe 2016
Munjal presents a simple way of building a scoreboard using the UVM infrastructure:
Munjal: Build an UVM scoreboard in few minutes
Verilab presented 2 papers at the SNUG 2016 conference. The first one
is about managing on the fly configurations of DUT using register model and configuration objects and the second one
is about how to view the coverage in SystemVerilog with the "glasses" of the 2012 revision of SystemVerilog standard and UVM.
Recommended Articles - September 2016
Keisuke Shimizu, from ClueLogic, explains in his UVM tutorial series, how you can use register callbacks to implement side effects inside the UVM register model: ClueLogic: UVM Tutorial for Candy Lovers – 36. Register Callbacks
Special attention should be payed to loop variables, as their behavior depends on how the array dimensions are specified at declaration: AMIQ Blog: Gotcha: The Behavior of Foreach Loop Variables Depends on How the Array Dimensions Are Specified
odel was initially developed for modeling and managing a SystemVerilog memory. AMIQ just released YAMM 2.0 which also includes the C++ implementation: AMIQ Blog: YAMM 2.0 Release is Available
Recommended Articles - August 2016
August is synonymous with vacation in many parts of the world, but not for everyone as you can see.
Cristian shows how to implement the mechanism which allows UVM registers to be sensitive to more than one reset signal:
CFSVision: SystemVerilog: How To Model Multiple Reset Signals in UVM Registers
Tudor has a quick look at the SVAUnit library
: VerificationGentleman: A Quick Look at SVAUnit
Manish started a series of tutorials on SystemVerilog OOP (Object Oriented Programming) concepts like: class, objects, class constructor, class properties/methods
, Copying Handles, copying objects, shallow copy, deep copy, static variables/methods
. They are a nice memory refreshment or a good starting point for people not used to OOP.
The latest article of the AMIQ - Gotcha series, illustrates what happens in SystemVerilog if static keyword is used both before and after the function or task keywords:
AMIQ - Gotcha: “static” function/task in SystemVerilog
Recommended Articles - July 2016
Manish Singhal, from LearnUVMVerification, presents a list of advantages of using assertions
and describes the arbitration mechanism of UVM Sequences
Keisuke Shimizu, from ClueLogic, shows how to dump transactions into a file using UVM do_record()
. He also gives an overview of component overrides
A short and practical article from Bryan Murdock on streaming an array of bytes into a "mismatched size" struct
e-language users receive an update: it is now possible to use non-constants inside bin definitions of a coverage item. See Fine Tuning of Coverage Model Definition.
As Specman is celebrating 20 years since its first introduction to the public, a good chance to recap Why Do We Need a Verification Language?
Recommended Articles - June 2016
Implementing coverage in SystemVerilog can become a challenging task. Horia presents the last article from a series of 3, on how to implement flexible coverage.
AMIQ: How to Implement Flexible Coverage Definitions (Part 3)
Henry Chan presents a high level overview of the uvm_reg
SemiEngineering: UVM Register Layer: The Structure
Here it is a funny way of explaining verification to a kid:
Gaurav Jalan: Learning Verification with Angry Birds
You should always use the macro `uvm_error() instead of uvm_report_error() function. Here's why:
Munjal: Be careful while writing UVM Report Messages
Keisuke Shimizu, from ClueLogic, shows how you can define/redefine the printing policy of UVM objects using do_print and uvm_printer:
ClueLogic: UVM Tutorial for Candy Lovers – 33. Defining do_print
CFSVision highlights a common mistake about naming scopes and constraints in SystemVerilog:
CFSVision: SystemVerilog Gotcha: In-line Constraints Scope
Recommended Articles - May 2016
Horia Enescu from AMIQ, started a series of posts that present how to implement flexible coverage definitions in SystemVerilog (Part 1
and Part 2
). Horia uses option.weight
-clause to allow coverage definitions to adapt to item's bin range.
New entry on our list
VerificationSudha encourages UVM dissection
and brings to surface internal information about UVM: Part I
and Part II
Error handling in serial communication
is a complex task and so is verifying it. If you are new to error scenarios, I definitely recommend reading these series of articles from VerificationSudha: understanding errors
, creating a plan and prioritize error scenarios
, defining error capabilities of the verification environment
, implementing error injection capability
, creating directed and random tests
and writing coverage for verification closure definition
Manish Singhal, from LearnUVMVerification wrote three more articles: UVM phasing
in UVM1.2, How to finish an UVM test
and what are the Debug tools within UVM
VerificationGentleman, continues his odyssey with SystemVerilog reflection API. In Part 1
he described how to create a reflection manager using DPI and VPI. In Part 2
he wrestles with language or compiler limitations, and in the end he achieves his goals to get and set the variables of a class.
Recommended Articles - April 2016
Ionut shares with us the highlights of DVCon-US 2016
conference. Ionut attended various presentations and also contributed an SVAUnit tutorial
"A picture is worth a thousand words". Stefan takes that principle and applies it on DUT data flows representation, so let the picture speak for itself:
How To Graphically Represent DUT’s Data Flows
Munjal continues to address topics from SystemVerilog and UVM. This time he focuses on killing a process in SystemVerilog
and using sub-phases and the phase jump concept from UVM
Keisuke Shimizu shows us how to customize message format in UVM 1.2
and how to use randc to generate all types of a sequence item
VerificationGentleman explores the implementation of a reflection mechanism in SystemVerilog:
VerificationGentleman: The Humble Beginnings of a SystemVerilog Reflection API
Handling reset when using UVM is an important task for a verification environment. CFSVision suggests one way of doing it:
CFSVision: SystemVerilog: How To Handle Reset In UVM
Efrat Shneydor shows a nice way of building generic scoreboards by using templates. Take a look and feel the full power of e-language constructs:
Cadence: Building Efficient Scoreboards
Recommended Articles March 2016
VerificationAcademy started to collect verification patterns on the Patterns Library
Mentor Graphics wrote an article
introducing this new page.
LearnUVMVerification explains in an intuitive way the UVM reporting
. They also provided us with Part 2
of "How virtual sequence works" (this is Part 1
in case you missed it).
Zeev Kirshenbaum/Cadence, presents in one of the Whiteboard Wednesday episode how stimulus can be driven to a DUT via a TLM 2.0 connection without prior knowledge of the protocol used by DUT:
Cadence: Whiteboard Wednesdays - Reusable Data-Driven Verification Using TLM 2.0
Cristian Slav/CFSVision, inspects the capabilities of SystemVerilog's "interface class" construct and proposes a way of emulating a multiple inheritance behavior:
Multiple Inheritance In SystemVerilog
Tudor Timisescu/VerificationGetleman, presents a way of ending an UVM test in a clean and safe way:
VerificationGentleman: An Overview of UVM End-of-Test Mechanisms
Stefan Birman/AMIQ presents How to Check Out-Of-Order Transactions
and plans to upload it as a new pattern on the VerificationAcademy's Patterns Library
Either you are a designer or not we advise you to read Jason Yu's compelling article about Clock Domain Crossing (CDC):
VerilogPro: Clock Domain Crossing Techniques – Part 1
Keisuke Shimizu/ClueLogic, enhances a previously designed driver in order to receive responses:
UVM Tutorial for Candy Lovers – 31. Provides Responses?
Specman Team/Cadence implemented a new extension to the e-language templates:
Cadence: e Templates – Cool Tool, Now Even Cooler
Recommended Articles - February 2016
Anders Nordstrom has written one of the best articles I've read about the effects of over-constraining properties in formal verification. The author describes what's safe to do and what's not safe to do when using formal methodologies:
EDN: Anders Nordstrom: Don’t over-constrain in formal property verification (FPV) flows
High speed serial communication protocols like Ethernet, RapidIO, DisplayPort, SATA etc. implement one or more of 8b/10b encoding, 64b/66b encoding or scrambling/descrambling in the Physical Coding Sublayer. AMIQ implemented these coding algorithms and shares them as Open Source with the Verification Community:
AMIQ Blog: Physical Coding Library
Verification Gentleman shows how to use UVM internals in order to register abstract classes with UVM factory:
VerificationGentleman:Registering Abstract Classes with the UVM Factory
FPGAs are not anymore what they used to be. I've recently attended an online presentation by Andrew Gardner via TVS Verification Future 2016 conference
is using FPGAs in an interesting manner. They've clustered together a lot of FPGAs to serve a common goal, that of emulating a very complex design consisting of multiple cores and various architectures. This farm of FPGAs makes it possible to verify complex designs which are otherwise impossible to be verified on simulation level. It's also cheaper to use FPGAs compared to hardware emulation
platforms provided by EDA companies. The difficult part in emulating such large designs using FPGAs is design partitioning and debug capabilities. Design partitioning needs to be done in a smart way so that updating the design affects as few FPGAs as possible. Debugging has also been improved in FPGAs with high bandwidth signal dumping capability. Another nice feature of ARMs FPGA farm is that they can remotely connect and control the FPGA farm.
I tried to offer a more detailed review, since the slides from the presentation are very much condensed and the main idea might be difficult to grasp without a live presentation of it. Here are the slides of the presentation:
ARM: FPGA accelerated IP Validation
All simulators provide these days transaction recording and visual analysis aids. Cristian presents how to use some of these features in order to speed-up debug:
CFSVision: Debugging Tip: Look At The Bubbles
A list of 7 YouTube videos on SystemVerilog and UVM from Synopsis:
Synopsis:Unleashing SystemVerilog and UVM (Series of 7 YouTube Videos)
Cadence has added in_table
constraints to e-language, a concise new language construct you can use, for example to specify a random configuration space:
Cadence: Using Tables to Handle Configurability in Incisive Enterprise Specman
UVM has a lot of features, some of them not commonly used. Munjals presents the 'uvm_barrier' and 'uvm_event' classes for tasks synchronization:
Munjalm: Synchronization using UVM features
Recommended Articles - January 2016
Automation can save precious time and, sometimes, neurons. Stefan proposes a way to automatize issue reporting and replication:
AMIQ Blog: How To Accelerate Issue Reporting and Replication
SystemVerilog's complexity is a "never-ending" source of inspiration for the gotchas series. This time the theme is "out of bounds indices":
AMIQ Blog: Gotcha: Access an out of Bounds Index for a SystemVerilog Fixed Size Array
Cristian has tapped into the same inspiration source. Here's how he explains sign extensions:
CFSVision: SystemVerilog Gotcha – Sign Extension
That's all for January! It seems holidays took their toll.
Recommended Articles - December 2015
One or more classes with the same name in different packages may lead to ambiguous log messages. Verification Gentleman found a way to avoid confusion.
VerificationGentleman: Packages, Class Names and UVM
AMIQ continues it's series of frameworks development and contributions to the verification community. This time a register model framework was developed mainly for the SystemC TLM models. It is written in C++ and it fills a gap in the SystemC modelling world. Don't hesitate to try it out in your project and let us know what do you think about it.
AMIQ Blog: C++ Register Modeling Framework
CFSVision presents a few simple rules for verifying an output signal.
CFSVision: How to Verify a DUT Output Signal
It might seem like this topic (Linux Environment Management) has nothing to do with hardware design and verification, but knowing how the linux environment works is among the first steps to create an easy to use infrastructure for hardware design and verification.
BryanMurdock: Linux Environment Management
Since this is my first "Recommended Articles" in 2016, I wish you a fulfilling new year!
Recommended Articles - November 2015
New entry on our list
: Basic Electronics Tutorials
From time to time, I need to refresh my electronics knowledge. One of my colleagues found Basic Electronics Tutorials
website, which explains a lot of the electronics concepts in a simple, straightforward way.
Yoav Hollander, inventor of the e-language
, brings into discussion the concept of "Verification" not only as ASIC/FPGA Hardware Verification, but as Verification in various other industries like military, servers, plants, urban, etc. He calls it Universal Verification Framework. It might look like a crazy idea but in ancient times flying machines were also seen as a crazy idea. You can follow his ideas on his blog called Foretellix:
Foretellix: Is a Universal Verification Framework possible?
The Verification Gentleman is once again on our list with 2 new articles. One about generating various combinations of burst sizes and burst combinations. And another about finding the best way to handle burst accesses to multiple registers.
VerificationGentleman:How Do I Transfer Thee? Let Me Count the Ways
VerificationGentleman: Accessing Multiple Registers at Once
Playing with e-language to solve interesting problems is always fun. Here is one such example:
AMIQ Blog: Einsten’s Five House Riddle – e-language Solution
AMIQ sponsored, contributed and attended this year's edition of DVCon Europe. Stefan Birman presents some of the highlights:
AMIQ Blog: DVCon Europe 2015 Highlights
Recommended Articles - October 2015
New entry on our list
, Jason Yu impressed us with his eloquent and easy to follow style. He shares his opinion on how Verilog constructs should be used:
VerilogPro: Verilog twins: case, casez, casex. Which Should I Use?
VerilogPro: One-hot State Machine in SystemVerilog – Reverse Case Statement
LearnUVMVerification presents the interaction between UVM driver and UVM sequences:
LearnUVMVerification: UVM Driver Use Models – Part 1
Stefan Birman presents his impressions on FDL Conference(Forum on specification and Design Languages):
AMIQ Blog: A Conference to Attend: Forum on Specification and Design Languages
had some fun trying to solve the Einstein's Five House Riddle in SystemVerilog and it seems that Sandeep Gor
followed along and made a solution for the e-language. I had taken Sandeep's challenge and found an optimized version for e-language which will be published soon on our blog.
DigitalVerification: Einstein’s Five House Riddle - Solution in 'e'
Recommended Articles - September 2015
SystemVerilog interfaces are rigid constructs that don't offer the flexibility of a class (e.g. polymorphism). Tudor Timisescu presents a recipe to create flavors of an interface, recipe which avoids turning the interface into a big, monolithic structure:
VerificationGentleman: On SystemVerilog Interface Polymorphism and Extendability
Did you ever think of functional coverage patterns
?Well, our colleague Stefan Birman created a reference list of functional bitwise coverage patterns:
AMIQ Blog: Functional Coverage Patterns: Bitwise Coverage
An interesting approach of Tudor Timisescu about centralization of SVA error messages from within an interface. Controlling error messages with a fine-granularity makes use of classes inside interfaces, macros and a report catcher together with a proxy concept:
VerificationGentleman: My Take on SVA Usage with UVM
Verification is about scenarios and if you want to be effective you need to stay high on the abstraction level. LearnUVMVerification shows how to take advantage of UVM Sequences by creating sequence hierarchies:
LearnUVMVerification: The way “UVM Hierarchical Sequences” works?
Cristian Slav, a former employee of AMIQ, started a new blog
on verification. In one of his articles he describes a way to translate aspect-oriented features encoded in e-language's DNA into a mix of SystemVerilog and design patterns:
CFSVision: How To Code Efficiently In SystemVerilog Without AOP
Recommended Articles - August 2015
Nicolaj Schweitz has compiled a metric-driven methodology that shall improve the testing capabilities in an Agile environment:
NicolajSchweitz: Can metrics improve agile testing? Measure, Analyse, Adjust
Rys Sommefeldt writes the story of chip development, a story where customers, engineers, tools, hardware, technologies and financial decisions take the stage:
RysSommefeldt: Semiconductors from idea to product
UVM tutorials flow did not stop on LearnUVMVerification. This time SystemVerilog data types
, UVM factory
and coverage metrics
are the main topics of interest.
AMIQ's Gotcha series continues. This time our focus is on SystemVerilog array indices. Having expressions as array indices may lead to unwanted behavior. Have a look at it:
AMIQ Blog - Gotcha: Using SystemVerilog Expressions as Array Indices
Recommended Articles - July 2015
Accellera Systems Initiative
and IEEE Standards Association
announced that UVM1.2 will be delivered as a contribution to the IEEE P1800.2™ standard. Check out Accellera's press release
for more details.
UVM is a methodology which creates opportunities. LearnUVMVerification
, a new entry on our radar, takes this opportunity and prepares a series of lessons that explore UVM. You can find graphical explanations for the mechanisms within UVM, like driver and sequencer interaction
, virtual interface and uvm_config_db
, UVM configuration object
, sequences and transactions
Last but not least Stefan Birman shares his experience of teaching a Hardware Verification Summer Course
to students of Department of Electronic Devices, Circuits and Architectures
, within Politehnica University of Bucharest
Recommended Articles – June 2015
For this June we have selected two articles:
An interesting discussion on the challenges of existing verification methodologies relative to the System Level verification requirements: Wrong Verification Revolution Offered
In case you wonder how to handle SystemVerilog coverage groups extensions here it is a good link: Some Ideas on Coverage Extendability
That's all for June.
Recommended Articles - May 2015
(ClueLogic) adds some sugar to the tasteless world of UVM messaging and serves it heavily garnished with pictures and detailed, well structured, explanations:
ClueLogic: UVM Tutorial for Candy Lovers – 27. Reporting Verbosity
ClueLogic: UVM Tutorial for Candy Lovers – 28. Message Logging
, inventor of vLang
, describes the effect of hiding a variable from the parent class with respect to polymorphism:
SystemVerilog.net: Variable hiding considered harmful
, a new entry on our radar, explains polymorphism:
SystemVerilogTips: Polymorphism in SystemVerilog
"hero" carries his own daemon that usually lurks on the last line in a modified block of a pasted code. Andrey Karpov
(Intel) lays out a convincing article about the peculiar last line
Intel: The Last Line Effect
connects the dots between coverage and constraints and presents a solution for keeping constraint and coverage ranges in sync with virtually no effort:
VerificationGentleman: Keeping Constraints and Covergroups in Sync
Be aware!!! This solution trespasses the separation of concerns and can hide generation constraints or coverage definition errors. As long as you implement generation and coverage as separate concerns you still have a chance to discover unintentional errors in either of them and/or in RTL. Molding coverage definitions to generation constraints eliminates the natural safety net of generation vs coverage implicit checking.
(AMIQ) reveals that randomization of object-type fields is achieved only if the object handle is not null:
AMIQ Blog: Gotcha: Using “rand” Modifier for Object Handles is not enough!
(Cadence, TeamSpecman) presents how to customize the behavior of a deep_copy() command from within e-Language code:
Cadence: Specman deep_copy()—Creating Too Many Structs
Recommended Articles - April 2015
Reading a specification is a continuous process that anyone can learn. Stefan guides you through the steps of this process:
AMIQ Blog: How to Read a Specification:
You can draw a picture without lifting the pencil by using constraint random generation:
VerificationGentleman: Fun and Games with CRV: Draw This Without Lifting Your Pencil
Writing assertions might be easy, but qualifying them it's a different story. SVAUnit is the framework that simplifies and speeds up the qualification process:
AMIQ Blog: How to Verify SystemVerilog Assertions with SVAUnit
To buy or not to buy a VIP? That is the question. Tudor explores a bit the possible answers:
VerificationGentleman: Cooking at Home or Eating Out? - The Pros and Cons of Homegrown VIP
Laxman Sahoo from ArrowDevices presents three scenarios in which the SystemVerilog threads are not OOP safe:
ArrowDevices: OOPs! 3 Issues That Show System Verilog Threads are Not OOP Safe!
Recommended Articles - March 2015
The Spring is here! We offer you a nice, hand-picked, bouquet of articles.
Sean Eron Anderson saves us from the marsh of bitwise operations. He compiled a list of techniques, algorithms, operations, functions that one could do to pull oneself up:
Standford: Bit Twiddling Hacks
The Gentleman presents his view on the good, ol' topic of "test's length":
VerificationGentleman: Less Is More - Why I Favor Short Tests
In another article he presents how one can override constraints using the mixin pattern
VerificationGentleman: Do You Want Sprinkles with That? - Mixing in Constraints
SystemVerilog is a source of inspiration by itself, it looks like we'll never lack gotchas:
AMIQ Blog: Gotcha: Function Calls in SystemVerilog Constraints
How do you protect against verification engineer's malpractice? Mark Litterick explores a solution in this dramatic presentation: Lies, Damned Lies, and Coverage
(or in article
Ashley Winn presents, on VerificationAcademy, how to implement flexible tests by using an organized sequence and test structure:
VerificationAcademy: Small, Maintainable Tests
AMIQ released first version of the SystemVerilog UVC for APB protocol:
AMIQ Blog: amiq_apb – SystemVerilog UVC for APB Protocol
Recommended Articles - February 2015
Although February was a 28 days month the Verification community was more active than on a 31 days month.
The random generation strategy could be the root cause of long time required to achieve coverage closure. Claudia provides a use case scenario for evaluating coverage closure in relation to generation strategy:
AMIQ Blog: A Coverage Closure Study: “on-the-fly” or “top-down” Generation?
Sudoku is fun! Solving it using SystemVerilog constraints multiplies that by 100:
Cluelogic: Hidden Gems of SystemVerilog – 3. Solving Sudoku
Wilson Rearch Group and their Functional Verification study is one-of-a kind study, the conclusions are always interesting and the 2014's results are no exception. In this first part they bring some insights about the FPGA design:
MentorGraphics, Part 1: The 2014 Wilson Research Group Functional Verification Study
An UVM compliant verification testbench, is a hierarchy of interacting UVM components that are required to work in different configuration settings. Synopsis shows several techniques where uvm_config_db is the key to propagate configuration among all components:
Synopsis: Hierarchal Testbench Configuration Using uvm_config_db
Accellera had initiated a new group that is focusing on a standard for portable stimulus. This is a brand new methodology that could contribute a lot to verification, especially in the "code reuse arena" among different verification levels. It's worth following the works of this new group:
Accellera: Accellera Systems Initiative Forms Portable Stimulus Working Group
Trent McClements, from Invionics, brings a new insight on SystemVerilog constructs always_latch
Invionics: SystemVerilog Insights: Do always_latch and always_ff provide any real value?
Keisuke Shimizu shows a basic code for connecting "candies" inside SystemVerilog with "candies" inside the C-code. One can raise one's blood's sugar level by reading:
ClueLogic: UVM Tutorial for Candy Lovers – 25. Using a C-Model
Bryan Murdock touches a sensitive subject: OpenSource vs EDA. What is the driving force for an Open Source project? Who writes Open Source code? Can Open Source take over the EDA industry? Find out part of the answers in here:
BryanMurdock: Why Open Source Has Not Taken Over EDA
Roman Shenkar explains why we might lose simulation cycles when connecting an event to a full signal bus instead of part of it:
Cadence - TeamSpecman: Don’t Lose Extra Simulation Cycles
Tudor Timisescu challenges the constraint solvers with a well known game, the N-Queens problem:
VerificationGentleman: Fun and Games with CRV: The N-Queens Problem
SystemVerilog might take you by surprise even when you are an experienced user. When you figure out the essence of the surprise, you may name it "a gotcha moment". Cristian Slav is going to show you a first gotcha in a series of such surprises:
AMIQ Blog: Gotcha: SystemVerilog’s post_randomize() is Called Top-Down Not Bottom-Up
Recommended Articles - January 2015
High speed serial protocols transmit or receive data on a 2xN-wire bus that usually does not include the clock signal. Each device must recover the clock out of the incoming data traffic. Deepak Nagaria explains how clock recovery works:
ArrowDevices: Beginners Guide To Clock Data Recovery
There are RTL designs which make use of two registers behind the same address (one register is used for read access and the other for the write access). How would you verify such a set of "twin registers"? See Tudor Timisescu's solution in his new article on the vr_ad register model series:
VerificationGentleman: vr_ad Twin Registers
Any IT passionate must have tried, at least once, sniffing the Ethernet link by using a network protocol analyzer. Wireshark is such a tool and Cristian Slav makes use of it in order to verify an RTL design or a VIP. As a test environment, Cristian uses the Ethernet library available on AMIQ's Github:
AMIQ Blog: How to Inspect Ethernet Packet Streams with Wireshark
Recommended Articles - December 2014
I wish our readers a 2015 filled up with personal and professional accomplishments!
Daniel Bayer from Cadence, brings the first article in a series that highlights constraint-modelling in Specman:
Cadence: Connected Field Sets – What Are Those and Why Should I Care?
Trent McClements from Invionics shows why combining macro definitions inside a package can be misleading:
Invionics: Packages and Macros Together? Watch Out!
Brian Murdock unfolds a long but true epic of how SystemVerilog's fork
constructs may bring headache to anyone using them:
Brian Murdock: SystemVerilog Fork Disable "Gotchas"
Recommended Articles - November 2014
Tudor recommends us to take advantage of the e-language features to define similar vr_ad registers instead of using copy/paste:
VerificationGentleman: Experimental Cures for Flattened Register Definitions in vr_ad
Then he shows us how to implement side effects of read/write operations using vr_ad's indirect_access()
VerificationGentleman: Using indirect_access(...) in vr_ad
The same Gentleman tutors us on how to handle multiple instances of vr_ad registers:
VerificationGentleman: Working with Multiple Instances of vr_ad Registers
Keisuke Shimizu helps you discover name space rules:
ClueLogic: Hidden Gems of SystemVerilog – 2. Name spaces
Cadence presents the power of e-language reflection in a 3 part series. This is a must read for juniors and seniors alike:
Cadence: Generic Dynamic Runtime Operations With e Reflection: Part 1 Part 2 Part3
Do you need an Ethernet packet library? Cristian provides the source code for SystemVerilog and SystemC:
AMIQ Blog: amiq_eth – The Ethernet Packet Library for SystemVerilog and SystemC
Daniel and Andra serve us a "Hello World!"-class tutorial on how to connect a SystemVerilog environment with Octave:
AMIQ Blog: How to Connect SystemVerilog with Octave
Get a glimpse and take the pulse of the first edition of DVCon Europe by reading Stefan's birds-eye (re)view:
AMIQ Blog: A Birds-Eye View of DVCon Europe
Here it is an easy way to decipher what timescale is used by RTL modules:
AMIQ Blog: How to print `timescale in Verilog, SystemVerilog and VHDL
Recommended Articles - October 2014
Working in a multi-language environment makes you hit this scenario: I model some data using a "when" subtype in e-language, how do I transfer that data over to a SystemVerilog component? The answer to the question is found here:
Cadence: Transferring e "when" Subtypes to UVM SV via TLM Ports—UVM-ML OA Package
When you wonder if a certain SystemVerilog language construct can reside inside another one use this article as your quick reference:
AMIQ Consulting Blog: What Goes where in SystemVerilog?
A common annoyance in SystemVerilog is making sure that enumerated type name (literals) are unique. Tudor presents a few ways to encapsulate enumerated type literals:
VerificationGentleman: A New Twist on SystemVerilog Enumerated Types
Recommended Articles - September 2014
SystemVerilog does not support multiple class inheritance, but there are ways to emulate it. Tudor Timisescu shows one way:
VerificationGentleman: Fake It 'til You Make It - Emulating Multiple Inheritance in SystemVerilog
Is your verification environment using multi-language verification components? Do you need to synchronize the end of test objections? Cadence illustrates how to sync the objection mechanism between verification components written in SystemVerilog and e-language:
Cadence: Objection Mechanism Synchronization Between SystemVerilog and e Active Verification Components
If you need backdoor UVM register access in SystemVerilog, this article is a good reference:
ClueLogic: UVM Tutorial for Candy Lovers – 24. Register Access through the Back Door
Ignoring bins from a cross coverage can be a tedious work if you don't know about some 2012 SystemVerilog constructs. Aurelian illustrates these constructs with some examples:
AMIQ Consulting Blog: How to Ignore Cross Coverage Bins Using Expressions in SystemVerilog
Recommended Articles – August 2014
A library for upgrading SystemVerilog’s capabilities. It handles file, string manipulation routines and more:
Verilab: Library code - svlib
Verilab: System Verilog, Batteries included
A library for enhancing SystemVerilog types and their pseudo-methods:
ClueLogic: CluLib Online Documentation
ClueLogic: ClueLib code
ClueLogic: Sharing Generic Class Libraries in SystemVerilog Makes Coding Fun Again
Article describing how to handle SV-VIP coverage customization, which also triggers the question: does SystemVerilog really cover verification needs?
VerificationHorizon: Increasing Verification Productivity Through Functional Coverage Management Automation
Learn what you should do and what you should NOT when implementing coverage in SystemVerilog:
VerificationHorizon: Functional Coverage Development Tips: Do’s and Don’ts
SystemVerilog goes online! You can now compile and run simulations in a web browser (log in with a google/facebook account):
EDA Playground: UVM example
EDA Playground: Home Page
Learn how to use 'interface class' construct, introduced in IEEE 1800-2012 standard. The author suggests that UVM library itself may benefit:
VerificationGentleman: SystemVerilog 2012 Has Even More 'Class'
Did you wonder why sometimes your e-code gets blocked in a 'sync' statement? Maya Bar explains shortly such a scenario:
Cadence: sync and wait Actions vs. Temporal Struct and Unit Members
Did you ever want to change the default behaviour of your simulator with respect to `uvm_error? Stop now, on first `uvm_error. AMIQ compiled a how to guide:
AMIQ Consulting Blog: How to Stop the Simulation on `uvm_error
Recommended Articles - July 2014
Zebra Puzzle is a very good didactic problem for understanding constraints. Tudor Timisescu, the blog's author, takes the effort in showing us what problems he encountered while building the constraints in SystemVerilog.
Verification Gentleman: Fun and Games with CRV: The Zebra Puzzle
If you want to know how to constraint elements of a dynamic array from System Verilog, here it is a place for a quick reference:
Verification Gentleman: The Not So Comprehensive Guide to SystemVerilog Array Constraints
Have you ever wondered what’s the finish criteria of a task when working with Agile methodology? Have you thought about using Kanban techniques in hardware verification? You can find some answers in this article:
AgileSOC: Kanban For One… The Verification Engineer Edition
A good exposure of clock-domain-crossing (CDC) verification challenges:
EDACafe Blogs: Fundamentals of Clock Domain Crossing Verification
A method to decrease the over-repeating painful effort in analyzing regression results:
AMIQ Consulting Blog: Save Time in Pre-Silicon Functional Verification Using Regression Automation Scripts
A hot discussion about how to determine programming languages’ productivity when writing code in HVL (Hardware Verification Languages) like e language or System Verilog language. Blake French, who started the topic tries to look into software world academics and extract measure points for HVLs. It’s interesting to see the feedback he got (you need a LinkedIn account):
LinkedIn Specman User Group: Productivity of Programming Languages
Are you done? The ultimate question a verification engineer receives from his/her manager:
AgileSOC: The 90% Done Myth