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December 7'th
2022
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Speaker
TBD Add description
TBD Add description
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March, 4'th
2021
Authors
Speaker
Functional verification using co-emulation has seen a growing trend due to its main advantage: testbench acceleration. Co-emulation requires two main things: (1) a connection between the host machine running the testbench and the hardware platform where the design is synthesized, and (2) a software component for interacting with the design. Most currently available solutions for achieving a complete co-emulation environment are proprietary.
This paper describes an Open-source Framework for Co-emulation (OFC) used for communication between a UVM-SystemVerilog testbench and a design emulated on the FPGA logic of a PYNQ board. The OFC framework is split into two main components: a TCP socket-based client-server connection and a Python component that interacts with the FPGA using the API provided by Xilinx for the PYNQ board. Owing to its modular implementation, the two components can be used either together or separately, depending on the user’s needs.
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October, 29'th
2019
Authors
Speaker
AMIQ Consulting developed the FC4SC library to complement existing C++ and SystemC libraries with the coverage collection that at the center of any modeling and verification project. Functional coverage lies at the core of semiconductor functional verification as the primary metric to assess quality and track the progress of the entire verification process. FC4SC provides mechanisms for functional coverage definition, collection, and reporting. It can be used in any application compliant with the C++ standard, starting with C++11, including SystemC models.
The primary use for the library is to measure the level of exercise of C++/SystemC verification models or C++ applications, checking which features were tested and which parameters were used during the test runs. Verification engineers can augment an existing C++/SystemC project with functional coverage to assess the quality and diversity of test suites. With this library, SystemC/C++ projects have an accurate way to track level of feature exercise and, therefore, the overall verification progress.
The FC4SC library is designed to interoperate with other tools and technologies, providing an application programming interface (API) that closely resembles functional coverage definition and usage defined by the IEEE 1800-2017 SystemVerilog standard. The collected data is saved in the Accellera Unified Coverage Interoperability Standard (UCIS) format for future interoperability with other coverage tools. Users can generate reports showing coverage holes, partially covered coverage bins, and other coverage analysis metrics.
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February, 25'th
2019
Authors
Speaker
AMIQ Consulting developed the FC4SC library to complement existing C++ and SystemC libraries with the coverage collection that at the center of any modeling and verification project. Functional coverage lies at the core of semiconductor functional verification as the primary metric to assess quality and track the progress of the entire verification process. FC4SC provides mechanisms for functional coverage definition, collection, and reporting. It can be used in any application compliant with the C++ standard, starting with C++11, including SystemC models.
The primary use for the library is to measure the level of exercise of C++/SystemC verification models or C++ applications, checking which features were tested and which parameters were used during the test runs. Verification engineers can augment an existing C++/SystemC project with functional coverage to assess the quality and diversity of test suites. With this library, SystemC/C++ projects have an accurate way to track level of feature exercise and, therefore, the overall verification progress.
The FC4SC library is designed to interoperate with other tools and technologies, providing an application programming interface (API) that closely resembles functional coverage definition and usage defined by the IEEE 1800-2017 SystemVerilog standard. The collected data is saved in the Accellera Unified Coverage Interoperability Standard (UCIS) format for future interoperability with other coverage tools. Users can generate reports showing coverage holes, partially covered coverage bins, and other coverage analysis metrics.
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October, 25'th
2018
Authors
Speaker
6.1 Portable Stimulus Driven SystemVerilog/UVM Verification Environment for the Verification of a High-capacity Ethernet Communication Endpoint
The scope of this paper is to present the steps taken and the challenges faced when using Portable Stimulus(PSS) as an abstraction layer on top of a SystemVerilog/UVM verification environment. The goal is the verification of a highly configurable, high-speed, communication endpoint, covering complex network scenarios and system-level corner cases. PSS is used in conjunction with SystemVerilog/UVM to increase verification efficiency by avoiding “scenario flooding” and keep a tight control of the verification space. All stimuli are defined in the test-bench and they are used to construct directed/random scenarios by utilizing a PSS generation model. The flow of the project in this case requires the SV/UVM VE to keep up with the guidelines for reusability while having an architecture that is compliant with the PSS mechanics of scenario generation. The paper addresses the possible issues and good practices discovered while implementing this verification strategy.
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October, 23'rd
2018
Authors
Speaker
Functional Coverage for SystemC(FC4SC) is a C++11 library that provides support for functional coverage collection by SystemC/C++ applications:
- SystemVerilog-like functional coverage constructs
- Functional coverage inspection API
- UCIS database support
- Coverage databse merge utilities
- HTML/JavaScript coverage report
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October, 21'st
2016
Authors
Speaker
Yet Another Memory Manager (YAMM) is a SystemVerilog library that provides support for memory based operations:
- Buffers can be allocated following 6 allocation modes with any granularity or address alignment
- Buffers can be inserted by user (non-overlapping)
- Buffers can be deallocated either by address or by handle
- Buffers can be searched for in the memory space by address or by handle
- Buffers support payload, which can be assigned by the user, randomly generated, read and compared.
- Implements a fast buffer search algorithm
Beside these features YAMM provides debug facilities (e.g. memory map dump, usage statistics) and it is easy to integrate it with existing verification environments.
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June, 28'th
2016
Authors
Speaker
Yet Another Memory Manager (YAMM) is a SystemVerilog library that provides support for memory based operations:
- Buffers can be allocated following 6 allocation modes with any granularity or address alignment
- Buffers can be inserted by user (non-overlapping)
- Buffers can be deallocated either by address or by handle
- Buffers can be searched for in the memory space by address or by handle
- Buffers support payload, which can be assigned by the user, randomly generated, read and compared.
- Implements a fast buffer search algorithm
Beside these features YAMM provides debug facilities (e.g. memory map dump, usage statistics) and it is easy to integrate it with existing verification environments.
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June, 23'rd
2016
Authors
Speaker
- Ionut Tolea
Yet Another Memory Manager (YAMM) is a SystemVerilog library that provides support for memory based operations:
- Buffers can be allocated following 6 allocation modes with any granularity or address alignment
- Buffers can be inserted by user (non-overlapping)
- Buffers can be deallocated either by address or by handle
- Buffers can be searched for in the memory space by address or by handle
- Buffers support payload, which can be assigned by the user, randomly generated, read and compared.
- Implements a fast buffer search algorithm
Beside these features YAMM provides debug facilities (e.g. memory map dump, usage statistics) and it is easy to integrate it with existing verification environments.
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February, 29'th
2016
Authors
Speaker
SystemVerilog Assertions(SVA) play a central role in functional verification of protocols, encompassing feature checking and coverage. In order to benefit from assertion advantages (fast, synthesizable, nonintrusive, coverable), we must verify that they pass or fail as described by the protocol specification. In turn this requires to implement the sequences of stimuli that properly trigger the assertion (making it pass or fail) and checks to ensure its correct behavior under the given conditions. We developed the SVAUnit framework with three objectives in mind:
- decouple SVA test logic from SVA definition
- simplify the creation of stimuli/checkers that validate the SVA
- simplify test and stimuli maintenance
SVAUnit is a simulator independent, UVM compliant package that combines the unit testing paradigm of the software world with the powerful feature of assertions from SystemVerilog.
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June, 25'th
2015
Authors
Speaker
SystemVerilog Assertions(SVA) play a central role in functional verification of protocols, encompassing feature checking and coverage. In order to benefit from assertion advantages (fast, synthesizable, nonintrusive, coverable), we must verify that they pass or fail as described by the protocol specification. In turn this requires to implement the sequences of stimuli that properly trigger the assertion (making it pass or fail) and checks to ensure its correct behavior under the given conditions. We developed the SVAUnit framework with three objectives in mind:
- decouple SVA test logic from SVA definition
- simplify the creation of stimuli/checkers that validate the SVA
- simplify test and stimuli maintenance
SVAUnit is a simulator independent, UVM compliant package that combines the unit testing paradigm of the software world with the powerful feature of assertions from SystemVerilog.
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June, 23'rd
2015
Authors
Speaker
SystemVerilog Assertions(SVA) play a central role in functional verification of protocols, encompassing feature checking and coverage. In order to benefit from assertion advantages (fast, synthesizable, nonintrusive, coverable), we must verify that they pass or fail as described by the protocol specification. In turn this requires to implement the sequences of stimuli that properly trigger the assertion (making it pass or fail) and checks to ensure its correct behavior under the given conditions. We developed the SVAUnit framework with three objectives in mind:
- decouple SVA test logic from SVA definition
- simplify the creation of stimuli/checkers that validate the SVA
- simplify test and stimuli maintenance
SVAUnit is a simulator independent, UVM compliant package that combines the unit testing paradigm of the software world with the powerful feature of assertions from SystemVerilog.
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April, 29'th
2015
Authors
Speaker
SystemVerilog Assertions(SVA) play a central role in functional verification of protocols, encompassing feature checking and coverage. In order to benefit from assertion advantages (fast, synthesizable, nonintrusive, coverable), we must verify that they pass or fail as described by the protocol specification. In turn this requires to implement the sequences of stimuli that properly trigger the assertion (making it pass or fail) and checks to ensure its correct behavior under the given conditions. We developed the SVAUnit framework with three objectives in mind:
- decouple SVA test logic from SVA definition
- simplify the creation of stimuli/checkers that validate the SVA
- simplify test and stimuli maintenance
SVAUnit is a simulator independent, UVM compliant package that combines the unit testing paradigm of the software world with the powerful feature of assertions from SystemVerilog.
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October, 14'th
2014
Authors
Speaker
Verification of high computational algorithmic RTL (e.g. digital signal processing) requires complex mathematical models that are hard to implement and slow to run in any of the existing hardware verification languages. Using numerical computing languages (e.g. Octave, Matlab) to code these models will dramatically speed up the verification sign-off by reuse of mathematical functions (e.g. predefined DSP functions) that are already verified. This also has a low risk of algorithm implementation bugs and guarantees optimal implementation for maximum simulation performance.
This paper illustrates typical usage of external mathematical models inside the verification environment using SystemVerilog as the verification language and Octave, an open source sibling of Matlab, as the numerical modeling language.
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May, 20'th
2014
Authors
Speaker
We do pre-silicon verification in multiple iterations, each iteration including at least a regression. Regressions consume a great deal of HW resources (e.g. CPU time) and SW resources (e.g. licenses) and… a lot of human effort. This is what usually happens when we run a regression: we aim to reduce the time spent in regression analysis, especially when we run regressions at a fast pace, for example overnight. We want to see the results in a simple, easy to read report, as soon as possible. We are eager to start debugging issues immediately, instead of aggregating and organizing those tons of information resulting from running a regression. We expect everyone in the team to keep up to date on the regression status with virtually no effort. And in the long run, we want to have a history of regression’s progress.
This poster shows a different way of dealing with these challenges using practical regression automation scripts. The scripts can help your team to save a lot of time and deal in an effective way with the regression results.
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May, 20'th
2014
Authors
Speaker
If you want to cover a bus activity you can either use bit toggling or define coverage ranges as power-of-2 intervals. As bit toggling is not very relevant (can be covered very quickly in one transition from 0 to MAX_VALUE) the second option is preferred. But using power-of-2 coverage creates another problem: coverage intervals are uneven and covering the smaller bins takes a lot of time. In large projects it can take weeks of regressions time to fill all of them.
This poster illustrates how the stimuli generation can be tweaked so that the smaller bins are hit just as often as the larger ones.
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