Stefan Birman

How to print `timescale in Verilog, SystemVerilog and VHDL

Sometimes you need to make sure the correct time unit and precision are applied for each module down the instance tree, especially when there are different timescale directives in different modules and timescale arguments are used. Print `timescale in Verilog, SystemVerilog Use $printtimescale(path) simulator directive: // timescale `timescale 1ns/10ps // top testbench module module tb(); […]

Stefan Birman

Attend Algorithm Verification Tutorial at DVCon Europe

We will be participating at DVCon Europe on October 14-15, 2014, in Munich. Two of our consultants will be presenting in the Tutorial section, on October 14, 2014 at 16:00. Daniel Ciupitu and Andra Socianu will guide you through efficient algorithm verification using SystemVerilog and Open Source Software. Beside the step-by-step tutorial, you will also […]

Stefan Birman

Meet AMIQ Consulting Panelists at CDNLive Munich

We are participating at CDNLive Munich on May 19-21, 2014. Two of our consultants will be presenting in the Canvas Conversations section, on May 20, 2014 at 12:00pm. Aurelian Munteanu will talk about how to use regression automation in order to speed-up regression analysis in “Be Fast, Stay Informed!” and Daniel Ciupitu, about how to […]