- Andra Socianu, Daniel Ciupitu
- Verification Engineers
How to Connect SystemVerilog with Octave
- November 21st, 2014
- 10 Comments
When we must verify a highly computational RTL, we may deal with complicated mathematical functions and algorithms. Implementing and debugging an RTL model can be tricky and time consuming. In such cases modeling using Octave/Matlab, C/C++ or SystemC can be a good alternative. In this article we present a “Hello world!” example to illustrate how […]
- DVCon , how to , Octave , SystemVerilog
- Stefan Birman
- Verification Engineer
How to print `timescale in Verilog, SystemVerilog and VHDL
- October 31st, 2014
- 2 Comments
Sometimes you need to make sure the correct time unit and precision are applied for each module down the instance tree, especially when there are different timescale directives in different modules and timescale arguments are used. Print `timescale in Verilog, SystemVerilog Use $printtimescale(path) simulator directive: // timescale `timescale 1ns/10ps // top testbench module module tb(); […]
- how to , SystemVerilog , Verilog , VHDL
- AMIQ Consulting
- Verification Engineer
How to Stop the Simulation on `uvm_error
- August 8th, 2014
- 2 Comments
The default behavior of `uvm_error is to continue the simulation once the message is reported. Although one can argue over Accelera’s default choice, there are ways to stop the simulation on `uvm_error. I’ve tested them with UVM 1.1d and UVM 1.2 releases. Using Simulator Arguments Major simulators support the +uvm_set_action command-line argument to set a […]
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