- Stefan Birman
- Verification Engineer
How to print `timescale in Verilog, SystemVerilog and VHDL
- October 31st, 2014
- 2 Comments
Sometimes you need to make sure the correct time unit and precision are applied for each module down the instance tree, especially when there are different timescale directives in different modules and timescale arguments are used. Print `timescale in Verilog, SystemVerilog Use $printtimescale(path) simulator directive: // timescale `timescale 1ns/10ps // top testbench module module tb(); […]
- how to , SystemVerilog , Verilog , VHDL
- Cristian Slav
- Verification Engineer
How to Stop the Simulation on `uvm_error
- August 8th, 2014
- 2 Comments
The default behavior of `uvm_error is to continue the simulation once the message is reported. Although one can argue over Accelera’s default choice, there are ways to stop the simulation on `uvm_error. I’ve tested them with UVM 1.1d and UVM 1.2 releases. Using Simulator Arguments Major simulators support the +uvm_set_action command-line argument to set a […]
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