- Aurelian Ionel Munteanu
- Verification Engineer
Recommended Articles – October 2014
- November 13th, 2014
- No Comments
Working in a multi-language environment makes you hit this scenario: I model some data using a “when” subtype in e-language, how do I transfer that data over to a SystemVerilog component? The answer to the question is found here: Cadence: Transferring e “when” Subtypes to UVM SV via TLM Ports—UVM-ML OA Package When you wonder […]
- AMIQ Consulting
- Verification Engineer
amiq_eth – The Ethernet Packet Library for SystemVerilog and SystemC
- November 10th, 2014
- No Comments
AMIQ released the amiq_eth verification library on GitHub, the hotspot for Open Source projects. The library is available to the verification community for free under the Apache License 2. The purpose of the amiq_eth library is to define all Ethernet packets as a basis for virtual verification IPs that target Ethernet upper layers. It includes […]
- Ethernet , functional verification , GitHub , SystemC , SystemVerilog , UVC , UVM , VIP
- Aurelian Ionel Munteanu
- Verification Engineer
Recommended Articles – September 2014
- October 9th, 2014
- No Comments
SystemVerilog does not support multiple class inheritance, but there are ways to emulate it. Tudor Timisescu shows one way: VerificationGentleman: Fake It ’til You Make It – Emulating Multiple Inheritance in SystemVerilog Is your verification environment using multi-language verification components? Do you need to synchronize the end of test objections? Cadence illustrates how to sync […]
- Aurelian Ionel Munteanu
- Verification Engineer
Recommended Articles – August 2014
- September 5th, 2014
- No Comments
A library for upgrading SystemVerilog’s capabilities. It handles file, string manipulation routines and more: Verilab: Library code – svlib Verilab: System Verilog, Batteries included A library for enhancing SystemVerilog types and their pseudo-methods: ClueLogic: CluLib Online Documentation ClueLogic: ClueLib code ClueLogic: Sharing Generic Class Libraries in SystemVerilog Makes Coding Fun Again Article describing how to […]
- AMIQ Consulting
- Verification Engineer
How to Stop the Simulation on `uvm_error
- August 8th, 2014
- 2 Comments
The default behavior of `uvm_error is to continue the simulation once the message is reported. Although one can argue over Accelera’s default choice, there are ways to stop the simulation on `uvm_error. I’ve tested them with UVM 1.1d and UVM 1.2 releases. Using Simulator Arguments Major simulators support the +uvm_set_action command-line argument to set a […]
- Florin Oancea
- Verification Engineer
Migrating to UVM 1.2
- June 6th, 2014
- 3 Comments
A couple of days ago I watched a presentation on UVM 1.2 by Tom Fitzpatrick of Mentor Graphics posted on Verification Academy, and I thought to give it a try and port one of our verification environments based on UVM 1.1d. Here is what my experience has been, originally posted on Accellera. 1. Download UVM […]
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