Stefan Birman

How To Graphically Represent DUT’s Data Flows

In this post I will explain how to analyse the DUT’s data flows and represent them graphically in an intuitive way. I use data flow analysis to create meaningful diagrams to be included in the verification specifications(e.g. see How To Read a Specification, section Read the spec with a meaningful goal). You won’t need more […]

Stefan Birman

How to Check Out-Of-Order Transactions

This article presents a general solution to the classic problem of checking out-of-order transactions. The main goal is to present the solution as a verification pattern that can be easily grasped and adapted to your verification project requirements (e.g. verification language, reference implementation language, design under test – DUT specifics etc.). The article’s sections are: […]

Stefan Birman

How To Accelerate Issue Reporting and Replication

This article presents a way to speed-up reporting and replication of issues. Every time you report an issue you need to include a description of the failing scenario, source code version information, simulation setup and steps required to reproduce the failure, the test and seed to run. The engineer assigned to fix the issue will […]

AMIQ Consulting

How to Verify SystemVerilog Assertions with SVAUnit

A version of this article, titled SystemVerilog Assertions Verification with SVAUnit, was presented at CDNLive EMEA 2015 by Andra Socianu and Ionut Ciocirlan. Intro SystemVerilog Assertions(SVA) play a central role in functional verification of protocols, encompassing feature checking and coverage. In order to benefit from assertion advantages (fast, synthesizeable, non-intrusive, coverable), we must verify they […]

Stefan Birman

How To Read a Specification

I consider that spec reading and comprehension is a critical part of the verification flow. All following stages in a verification project depend on this activity and that’s why every junior engineer who joins AMIQ goes first through a specification reading crash course. I present below a set of guidelines that AMIQ engineers follow. Enjoy! […]

Andra Socianu, Daniel Ciupitu

How to Connect SystemVerilog with Octave

When we must verify a highly computational RTL, we may deal with complicated mathematical functions and algorithms. Implementing and debugging an RTL model can be tricky and time consuming. In such cases modeling using Octave/Matlab, C/C++ or SystemC can be a good alternative. In this article we present a “Hello world!” example to illustrate how […]