Recommended Articles

Recommended Articles – May 2016

Horia Enescu from AMIQ, started a series of posts that present how to implement flexible coverage definitions in SystemVerilog (Part 1 and Part 2). Horia uses option.weight and with-clause to allow coverage definitions to adapt to item’s bin range. New entry on our list VerificationSudha encourages UVM dissection and brings to surface internal information about […]

AMIQ Education Program

Hardware Verification Summer Course at Politehnica University of Bucharest

Between 20th and 31st of July I taught an intensive hardware verification course organized by the Department of Electronic Devices, Circuits and Architectures, within Politehnica University of Bucharest. This course is a pilot for introducing verification in the department’s curriculum. In January 2015 I met Professor Gheorghe M. Stefan and Assistant Professors Lucian Petrica and […]

AMIQ Consulting

SVAUnit 2.0 Release is Available

AMIQ is pleased to announce version 2.0 of the SVAUnit framework! Highlights of SVAUnit 2.0 release are: Support for sequence based scenarios Upgraded test setup API Support for complex topologies VPI-related API accessible through a wrapper class pre_test() task is now deprecated UVM compliance reinforced using the Verissimo SystemVerilog Testbench Linter SNUG-2015 paper included Let’s go […]

AMIQ Consulting

How to Verify SystemVerilog Assertions with SVAUnit

A version of this article, titled SystemVerilog Assertions Verification with SVAUnit, was presented at CDNLive EMEA 2015 by Andra Socianu and Ionut Ciocirlan. Intro SystemVerilog Assertions(SVA) play a central role in functional verification of protocols, encompassing feature checking and coverage. In order to benefit from assertion advantages (fast, synthesizeable, non-intrusive, coverable), we must verify they […]

Stefan Birman

How To Read a Specification

I consider that spec reading and comprehension is a critical part of the verification flow. All following stages in a verification project depend on this activity and that’s why every junior engineer who joins AMIQ goes first through a specification reading crash course. I present below a set of guidelines that AMIQ engineers follow. Enjoy! […]

AMIQ Consulting

amiq_dcr – SystemVerilog UVC for DCR Protocol

AMIQ released the amiq_dcr UVC on GitHub The UVC is available to the verification community for free under the Apache License 2. The purpose of the amiq_dcr UVC is to model the Device Control Register Bus (DCR) protocol, supporting all the features of the protocol such as: 4-cycle minimum read or write transfers extendable by […]