Recommended Articles

Recommended Articles – September 2015

SystemVerilog interfaces are rigid constructs that don’t offer the flexibility of a class (e.g. polymorphism). Tudor Timisescu presents a recipe to create flavors of an interface, recipe which avoids turning the interface into a big, monolithic structure: VerificationGentleman: On SystemVerilog Interface Polymorphism and Extendability Did you ever think of functional coverage patterns?Well, our colleague Stefan […]

Stefan Birman

Functional Coverage Patterns: Bitwise Coverage

As you probably already know, all digital design circuits either process or transfer data, which is usually represented as a bit vector of size N. Data values that pass through the system provide an indication of how system’s functionality is exercised, so you need to add them to the functional coverage goals. You might ask […]

Recommended Articles

Recommended Articles – March 2015

The Spring is here! We offer you a nice, hand-picked, bouquet of articles. Sean Eron Anderson saves us from the marsh of bitwise operations. He compiled a list of techniques, algorithms, operations, functions that one could do to pull oneself up: Standford: Bit Twiddling Hacks The Gentleman presents his view on the good, ol’ topic […]

Claudia Iancu

A Coverage Closure Study: “on-the-fly” or “top-down” Generation?

Recently, I’ve verified how a DUT tolerates inter-packet delays. Basically, I’ve driven a fixed number of packets with the following constraints: Each inter-packet delay must not exceed a maximum inter-packet delay value The sum of all inter-packet delays must be equal with a specified window delay value At first glance, the most interesting cases appear […]

Recommended Articles

Recommended Articles – September 2014

SystemVerilog does not support multiple class inheritance, but there are ways to emulate it. Tudor Timisescu shows one way: VerificationGentleman: Fake It ’til You Make It – Emulating Multiple Inheritance in SystemVerilog Is your verification environment using multi-language verification components? Do you need to synchronize the end of test objections? Cadence illustrates how to sync […]

Aurelian Ionel Munteanu

How to Ignore Cross Coverage Bins Using Expressions in SystemVerilog

Lately, I’ve been playing with the coverage features of SystemVerilog. One thing I wanted to do was to filter out some bins from the auto-generated list of cross bins. I searched the Internet for a solution, but only found similar questions with no clear answers. Therefore, I started to work on this problem and came […]