Recommended Articles

Recommended Articles – January 2015

High speed serial protocols transmit or receive data on a 2xN-wire bus that usually does not include the clock signal. Each device must recover the clock out of the incoming data traffic. Deepak Nagaria explains how clock recovery works: ArrowDevices: Beginners Guide To Clock Data Recovery There are RTL designs which make use of two […]

Recommended Articles

Recommended Articles – November 2014

Tudor recommends us to take advantage of the e-language features to define similar vr_ad registers instead of using copy/paste: VerificationGentleman: Experimental Cures for Flattened Register Definitions in vr_ad Then he shows us how to implement side effects of read/write operations using vr_ad’s indirect_access() method: VerificationGentleman: Using indirect_access(…) in vr_ad The same Gentleman tutors us on […]

Recommended Articles

Recommended Articles – October 2014

Working in a multi-language environment makes you hit this scenario: I model some data using a “when” subtype in e-language, how do I transfer that data over to a SystemVerilog component? The answer to the question is found here: Cadence: Transferring e “when” Subtypes to UVM SV via TLM Ports—UVM-ML OA Package When you wonder […]

Daniel Ciupitu

Coverage Aware Generation using e Language Normal Distribution Constraints

When defining coverage items we need to make a trade-off between the number of coverage buckets, their size and the simulation time required to get them covered. From our experience the solution is to generate items being aware of how they will be covered. For example if the coverage item has power-of-2 buckets, the generated […]