Recommended Articles

Recommended Articles – July 2015

Accellera Systems Initiative and IEEE Standards Association announced that UVM1.2 will be delivered as a contribution to the IEEE P1800.2™ standard. Check out Accellera’s press release for more details. UVM is a methodology which creates opportunities. LearnUVMVerification, a new entry on our radar, takes this opportunity and prepares a series of lessons that explore UVM. […]

AMIQ Education Program

Hardware Verification Summer Course at Politehnica University of Bucharest

Between 20th and 31st of July I taught an intensive hardware verification course organized by the Department of Electronic Devices, Circuits and Architectures, within Politehnica University of Bucharest. This course is a pilot for introducing verification in the department’s curriculum. In January 2015 I met Professor Gheorghe M. Stefan and Assistant Professors Lucian Petrica and […]

AMIQ Consulting

amiq_dcr – SystemVerilog UVC for DCR Protocol

AMIQ released the amiq_dcr UVC on GitHub The UVC is available to the verification community for free under the Apache License 2. The purpose of the amiq_dcr UVC is to model the Device Control Register Bus (DCR) protocol, supporting all the features of the protocol such as: 4-cycle minimum read or write transfers extendable by […]

AMIQ Consulting

amiq_apb – SystemVerilog UVC for APB Protocol

We release amiq_apb UVC to the verification community under the Apache License 2. amiq_apb UVC implements the APB protocol and it features: Supports the full APB protocol specification: one master-multiple slaves, transfers with wait states, slave error response, access protection HTML API documentation included Verification plans included Self checking tests Usage examples UVM-1.2 Compliant We […]

Recommended Articles

Recommended Articles – February 2015

Although February was a 28 days month the Verification community was more active than on a 31 days month. The random generation strategy could be the root cause of long time required to achieve coverage closure. Claudia provides a use case scenario for evaluating coverage closure in relation to generation strategy: AMIQ Blog: A Coverage […]

Recommended Articles

Recommended Articles – October 2014

Working in a multi-language environment makes you hit this scenario: I model some data using a “when” subtype in e-language, how do I transfer that data over to a SystemVerilog component? The answer to the question is found here: Cadence: Transferring e “when” Subtypes to UVM SV via TLM Ports—UVM-ML OA Package When you wonder […]