Recommended Articles

Recommended Articles – June 2017

UVM provides callbacks mechanism that allows one to expand code’s functionality. Munjal explains advanced usage of callbacks in UVM. You might remember, from the highlights of DVCon US 2017 conference, that we recommended a paper about constrained random and dynamic seed manipulation (“Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding […]

Horia-Răzvan Enescu

How to Unpack Data Using the SystemVerilog Streaming Operators (>>, <<)

In this post I show how to use the streaming operators to unpack data into variables or data structures in SystemVerilog. This is the second part of a 3-post series on data packing/unpacking operations and the natural follow-up to the first part that focuses on packing data using streaming operators. The unpacking operation is the […]

Recommended Articles

Recommended Articles – May 2017

Yet another way of connecting the testbench components to the interface containing the signals. Learn more about accessor classes and parametrization in the article How To Reduce the Number of VIP Instances using Accessor Classes We have a new entry on our radar: VerificationLand. Mark Glasser displays his view of an SVlogical way of writing […]

Horia-Răzvan Enescu

How to Pack Data Using the SystemVerilog Streaming Operators (>>, <<)

The verification of digital circuits requires dealing with bits and bytes. It is not a trivial thing to pack or unpack bits, bytes, half words, words or user defined data structures. This post is the first in a series of tutorials about packing and unpacking in SystemVerilog. The article’s sections are: Introduction 1. Pack bytes […]

Stefan Birman

How To Reduce the Number of VIP Instances using Accessor Classes

In this post I demonstrate how to use parameterization and accessor classes in order to reduce a variable number of VIP instances to a single VIP instance. The implementation I describe might improve the overall performance of the verification environment by reducing the number of threads and the amount of maintenance required (e.g. fewer instances, […]

Recommended Articles

Recommended Articles – April 2017

There are multiple ways of connecting a SystemVerilog interface instance to a virtual interface inside the verification environment. Cristian, described two ways of doing just that. One good old simple way when having just one interface instance and another one for multiple instances. CFSVision: UVM: How to Pass a Virtual Interface from Testbentch to Environment […]