Recommended Articles

Recommended Articles – February 2020

After a long pause, Tudor Timisescu wrote a new post about compilation time of SystemVerilog code and how it is impacted by the code aggregation in SystemVerilog packages. Under certain conditions, changing a single file might result in recompilation of the whole code. Find out why in Bigger Is Not Always Better: Builds Are Faster […]

Recommended Articles

Recommended Articles – January 2020

A bit of history on how DMA (Direct Memory Access) works. Despite being 6 years old, it worth the lecture: An overview of direct memory access What is open-source hardware? If you had the same question, you might be interested in this article: Open source hardware risks. Also, the article brought to my attention the […]

Recommended Articles

Recommended Articles – December 2019

In early 2018, AMIQ released a new library called FC4SC (Functional Coverage for SystemC). The community responded in a positive manner and started to evaluate it and asked for improvements. Late this year, the library has been donated to Accellera in order to fill the functional coverage gap from the SystemC world. More on the […]

Dragos Dospinescu

AMIQ Consulting Contributes C++ Coverage Library to Accellera

We have posted before about the Functional Coverage for SystemC (FC4SC) library that we developed and made available to the semiconductor industry. We are pleased to report that the Accellera Systems Initiative standards organization has accepted our donation of FC4SC for use by their SystemC Verification Working Group. Since we released FC4SC as open source, […]

Recommended Articles

Recommended Articles – November 2019

A while ago, the Specman team announced that you may now take advantage of Python in the e-language world. Lately, the same team has described one of the possible applications which makes use of this Python support. For example you can now analyze your coverage results using Python. Can you imagine another kind of application? […]

Recommended Articles

Recommended Articles – September 2019

Did you ever had the need to programmatically dump the values of signals from a simulation? SystemVerilog offers such a dumping capability by means of system tasks. The signal values are dumped into a vcd (value change dump) file. The vcd files can later be read by a waveform viewer and examine signals’ behavior. Read […]