Recommended Articles

Recommended Articles – August 2018

In his article about how to avoid FIFO overflows, Stefan promised a second solution. Here is part II of the article presenting the solution which makes use of uvm constructs. Neil from AgileSOC continues to simplify the SVAUnit framework. He makes use of his new mocking framework in order to decouple the driver from the […]

Stefan Birman

How To Protect FIFOs Against Overflow – Part 2

This post is a follow-up of the How To Protect FIFOs Against Overflow – Part 1 and it details the second proposed solution. The complete implementation presented in this post can be downloaded from GitHub. That being said, let’s go through the implementation, step-by-step. Step 1. Define enumeration items that identify the two FIFOs typedef […]

Recommended Articles

Recommended Articles – July 2018

AMIQ Education Program saga continues…. This years’ summer school received more attention from the students according to Stefan’s feedback: Digital Circuits Simulation and Verification Summer School. FIFOs are encountered in many digital designs and the verification of such designs comes with specific challenges, one of them being to protect the FIFOs against overflow. You can […]

Stefan Birman

How To Protect FIFOs Against Overflow – Part 1

Systems containing FIFOs face verification engineers with a “classic” black-box verification problem: how to protect FIFOs against overflow in order to avoid unpredictable loss of packets. The difficulty in solving this problem comes from the lack of visibility into DUT’s internal states, which means the solution should count only on the events/packets driven/monitored on the […]

AMIQ Education Program

Digital Circuits Simulation and Verification Summer School

The 2018 Digital Circuits Simulation and Verification Summer School took place 9th-13th of July. There were 16 participants, a big step forward compared to previous editions. The course setup was similar with the 2017 one: 8 hours a day for 5 days, same place, same device under test, similar introduction into verification theory. Students used […]

Recommended Articles

Recommended Articles – June 2018

We present to you the SystemVerilog and VHDL Grammars in HTML format. The grammars represent the BNF (Backus-Naur Form) notation in an HTML format, with hyperlinks, anchors and tooltips. You can also download them from the GitHub repository. John Neil, from AgileSOC, continues his reflection on how verification engineers should think about their testbench code: […]