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Gotcha: Function Calls in SystemVerilog Constraints

SystemVerilog allows to call functions inside constraints, although, as I found out, it is a sensitive topic. Here is an example: class constraint_container; rand int unsigned a, b, c; function int unsigned get_a(); return a; endfunction function int unsigned value_of(int unsigned value); return value; endfunction constraint a_constraint { a == 5; // I expect “b” […]

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Gotcha: SystemVerilog’s post_randomize() is Called Top-Down Not Bottom-Up

SystemVerilog classes contain the pre-defined function post_randomize(), which is automatically called at the end of the randomization. One can override this function to do extra processing after randomization. In SystemVerilog post_randomize() is called top-down and not bottom-up! The top-down call of post_randomize() is counter-intuitive, especially for those of you in love with e-Language, and it […]

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Recommended Articles – January 2015

High speed serial protocols transmit or receive data on a 2xN-wire bus that usually does not include the clock signal. Each device must recover the clock out of the incoming data traffic. Deepak Nagaria explains how clock recovery works: ArrowDevices: Beginners Guide To Clock Data Recovery There are RTL designs which make use of two […]

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A Coverage Closure Study: “on-the-fly” or “top-down” Generation?

Recently, I’ve verified how a DUT tolerates inter-packet delays. Basically, I’ve driven a fixed number of packets with the following constraints: Each inter-packet delay must not exceed a maximum inter-packet delay value The sum of all inter-packet delays must be equal with a specified window delay value At first glance, the most interesting cases appear […]

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Recommended Articles – December 2014

I wish our readers a 2015 filled up with personal and professional accomplishments! Daniel Bayer from Cadence, brings the first article in a series that highlights constraint-modelling in Specman: Cadence: Connected Field Sets – What Are Those and Why Should I Care? Trent McClements from Invionics shows why combining macro definitions inside a package can […]

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How to Inspect Ethernet Packet Streams with Wireshark

Many protocol stacks in SoCs are based on the IEEE 802.3 Ethernet protocol as the data link layer, while the upper layers can be standard or application specific. Therefore, verification engineers have to inspect and debug Ethernet packet streams generated or monitored by the verification environment. This article shows how to connect the Wireshark network […]