Recommended Articles

Recommended Articles – July 2016

Manish Singhal, from LearnUVMVerification, presents a list of advantages of using assertions and describes the arbitration mechanism of UVM Sequences. Keisuke Shimizu, from ClueLogic, shows how to dump transactions into a file using UVM do_record(). He also gives an overview of component overrides in UVM. A short and practical article from Bryan Murdock on streaming […]

AMIQ Education Program

Digital Circuits Simulation and Verification Summer Course 2.0

Well, well. The Summer Course saga continues… Between 27th of June and 8th of July I delivered the Digital Circuits Simulation and Verification Course organized by the Department of Electronic Devices, Circuits and Architectures, within Politehnica University of Bucharest. This course was an improved version of the 2015’s Summer School. This year I was better […]

Ionuț Ciocîrlan

Highlights of DVCon US 2016

DVCon US (Feb. 29th – Mar 3rd, 2016, San Jose, California) has concluded another successful edition. There were a lot of interesting tutorials, panels and technical sessions, with SV/UVM still being a major focus. There was also a clear emphasis on portable stimuli and the associated standard developed by Accellera’s Portable Stimuli Working Group (PSWG), […]

Recommended Articles

Recommended Articles – February 2016

Anders Nordstrom has written one of the best articles I’ve read about the effects of over-constraining properties in formal verification. The author describes what’s safe to do and what’s not safe to do when using formal methodologies: EDN: Anders Nordstrom: Don’t over-constrain in formal property verification (FPV) flows High speed serial communication protocols like Ethernet, […]

Recommended Articles

Recommended Articles – October 2015

New entry on our list, Jason Yu impressed us with his eloquent and easy to follow style. He shares his opinion on how Verilog constructs should be used: VerilogPro: Verilog twins: case, casez, casex. Which Should I Use? VerilogPro: One-hot State Machine in SystemVerilog – Reverse Case Statement LearnUVMVerification presents the interaction between UVM driver […]

Recommended Articles

Recommended Articles – September 2015

SystemVerilog interfaces are rigid constructs that don’t offer the flexibility of a class (e.g. polymorphism). Tudor Timisescu presents a recipe to create flavors of an interface, recipe which avoids turning the interface into a big, monolithic structure: VerificationGentleman: On SystemVerilog Interface Polymorphism and Extendability Did you ever think of functional coverage patterns?Well, our colleague Stefan […]