Recommended Articles

Recommended Articles – September 2020

Did you know that you can match strings using regular expressions from within SystemVerilog code? UVM implements a function called uvm_re_match. My colleague, Florin Oancea, explains how to use it and what you should pay attention at: How to Match Strings in SystemVerilog Using Regular Expressions In the August edition of the recommended articles I […]

Florin Oancea

How to Match Strings in SystemVerilog Using Regular Expressions

Recently, I needed to filter out some instance paths from my UVM testbench hierarchy. I discovered that this can be done using regular expressions and that UVM already has a function called uvm_pkg::uvm_re_match(), which is a DPI-C function that makes use of the POSIX function regexec() to perform a string match. The uvm_re_match function will […]

Recommended Articles

Recommended Articles – August 2020

Ioana Cristea from Amiq shows how to achieve a non blocking communication between the SystemVerilog simulator and an external component, like Python: Non-Blocking Socket Communication in SystemVerilog Using DPI-C. Neil Johnson and Dave Rich have launched a challenge to the verification community. Discover and fix race conditions inside 10 SystemVerilog code snippets. Read more in […]

Ioana Catalina Cristea

Non-Blocking Socket Communication in SystemVerilog Using DPI-C

As discussed in a previous article (How to Connect SystemVerilog with Python), functional verification may require an interaction between the testbench and components written in various programming languages. The above-mentioned post describes a method for connecting SystemVerilog with Python that assumes a one-to-one relationship between the sent and received packets. This implies that the communication […]

Recommended Articles

Recommended Articles – July 2020

Neil Johnson announced he will take a step back and pass the leadership of SVUnit project to Tudor Timisescu, aka Verification Gentleman. SVUnit is a consistent and valuable contribution to the verification community and I am happy it is not lost. That’s the OpenSource spirit at work! Welcome back Manish! After four years of silence, […]

Recommended Articles

Recommended Articles – June 2020

SystemVerilog Multidimensional Arrays is a juicy topic for a blog post given they are feature reach. Here is a post that explains some of the features: SystemVerilog Multidimensional Arrays A long-awaited feature comes into existence: adjusting verification environment behavior based on collected coverage items in real time at run time. Specman team facilitates this operation […]