Recommended Articles

Recommended Articles – September 2014

SystemVerilog does not support multiple class inheritance, but there are ways to emulate it. Tudor Timisescu shows one way: VerificationGentleman: Fake It ’til You Make It – Emulating Multiple Inheritance in SystemVerilog Is your verification environment using multi-language verification components? Do you need to synchronize the end of test objections? Cadence illustrates how to sync […]

Alexandru Marin

What Goes where in SystemVerilog?

Is it legal SystemVerilog syntax to declare a class inside a program? What about a function inside a generate block? The table below summarizes the syntactically legal combinations (marked with a check ✔ sign). The number of possible combinations is astonishing. And yet I bet some of the valid combinations have never crossed your mind! On the […]

Aurelian Ionel Munteanu

How to Ignore Cross Coverage Bins Using Expressions in SystemVerilog

Lately, I’ve been playing with the coverage features of SystemVerilog. One thing I wanted to do was to filter out some bins from the auto-generated list of cross bins. I searched the Internet for a solution, but only found similar questions with no clear answers. Therefore, I started to work on this problem and came […]

Recommended Articles

Recommended Articles – August 2014

A library for upgrading SystemVerilog’s capabilities. It handles file, string manipulation routines and more: Verilab: Library code – svlib Verilab: System Verilog, Batteries included A library for enhancing SystemVerilog types and their pseudo-methods: ClueLogic: CluLib Online Documentation ClueLogic: ClueLib code ClueLogic: Sharing Generic Class Libraries in SystemVerilog Makes Coding Fun Again Article describing how to […]

Cristian Slav

How to Stop the Simulation on `uvm_error

The default behavior of `uvm_error is to continue the simulation once the message is reported. Although one can argue over Accelera’s default choice, there are ways to stop the simulation on `uvm_error. I’ve tested them with UVM 1.1d and UVM 1.2 releases. Using Simulator Arguments Major simulators support the +uvm_set_action command-line argument to set a […]

Recommended Articles

Recommended Articles – July 2014

Zebra Puzzle is a very good didactic problem for understanding constraints. Tudor Timisescu, the blog’s author, takes the effort in showing us what problems he encountered while building the constraints in SystemVerilog. Verification Gentleman: Fun and Games with CRV: The Zebra Puzzle If you want to know how to constraint elements of a dynamic array […]