Recommended Articles

Recommended Articles – January 2015

High speed serial protocols transmit or receive data on a 2xN-wire bus that usually does not include the clock signal. Each device must recover the clock out of the incoming data traffic. Deepak Nagaria explains how clock recovery works: ArrowDevices: Beginners Guide To Clock Data Recovery There are RTL designs which make use of two […]

Recommended Articles

Recommended Articles – December 2014

I wish our readers a 2015 filled up with personal and professional accomplishments! Daniel Bayer from Cadence, brings the first article in a series that highlights constraint-modelling in Specman: Cadence: Connected Field Sets – What Are Those and Why Should I Care? Trent McClements from Invionics shows why combining macro definitions inside a package can […]

Recommended Articles

Recommended Articles – November 2014

Tudor recommends us to take advantage of the e-language features to define similar vr_ad registers instead of using copy/paste: VerificationGentleman: Experimental Cures for Flattened Register Definitions in vr_ad Then he shows us how to implement side effects of read/write operations using vr_ad’s indirect_access() method: VerificationGentleman: Using indirect_access(…) in vr_ad The same Gentleman tutors us on […]

Recommended Articles

Recommended Articles – October 2014

Working in a multi-language environment makes you hit this scenario: I model some data using a “when” subtype in e-language, how do I transfer that data over to a SystemVerilog component? The answer to the question is found here: Cadence: Transferring e “when” Subtypes to UVM SV via TLM Ports—UVM-ML OA Package When you wonder […]

Recommended Articles

Recommended Articles – September 2014

SystemVerilog does not support multiple class inheritance, but there are ways to emulate it. Tudor Timisescu shows one way: VerificationGentleman: Fake It ’til You Make It – Emulating Multiple Inheritance in SystemVerilog Is your verification environment using multi-language verification components? Do you need to synchronize the end of test objections? Cadence illustrates how to sync […]

Recommended Articles

Recommended Articles – August 2014

A library for upgrading SystemVerilog’s capabilities. It handles file, string manipulation routines and more: Verilab: Library code – svlib Verilab: System Verilog, Batteries included A library for enhancing SystemVerilog types and their pseudo-methods: ClueLogic: CluLib Online Documentation ClueLogic: ClueLib code ClueLogic: Sharing Generic Class Libraries in SystemVerilog Makes Coding Fun Again Article describing how to […]