Recommended Articles

Recommended Articles – November 2014

Tudor recommends us to take advantage of the e-language features to define similar vr_ad registers instead of using copy/paste: VerificationGentleman: Experimental Cures for Flattened Register Definitions in vr_ad Then he shows us how to implement side effects of read/write operations using vr_ad’s indirect_access() method: VerificationGentleman: Using indirect_access(…) in vr_ad The same Gentleman tutors us on […]

Recommended Articles

Recommended Articles – October 2014

Working in a multi-language environment makes you hit this scenario: I model some data using a “when” subtype in e-language, how do I transfer that data over to a SystemVerilog component? The answer to the question is found here: Cadence: Transferring e “when” Subtypes to UVM SV via TLM Ports—UVM-ML OA Package When you wonder […]

Recommended Articles

Recommended Articles – September 2014

SystemVerilog does not support multiple class inheritance, but there are ways to emulate it. Tudor Timisescu shows one way: VerificationGentleman: Fake It ’til You Make It – Emulating Multiple Inheritance in SystemVerilog Is your verification environment using multi-language verification components? Do you need to synchronize the end of test objections? Cadence illustrates how to sync […]

Aurelian Ionel Munteanu

How to Ignore Cross Coverage Bins Using Expressions in SystemVerilog

Lately, I’ve been playing with the coverage features of SystemVerilog. One thing I wanted to do was to filter out some bins from the auto-generated list of cross bins. I searched the Internet for a solution, but only found similar questions with no clear answers. Therefore, I started to work on this problem and came […]

Recommended Articles

Recommended Articles – August 2014

A library for upgrading SystemVerilog’s capabilities. It handles file, string manipulation routines and more: Verilab: Library code – svlib Verilab: System Verilog, Batteries included A library for enhancing SystemVerilog types and their pseudo-methods: ClueLogic: CluLib Online Documentation ClueLogic: ClueLib code ClueLogic: Sharing Generic Class Libraries in SystemVerilog Makes Coding Fun Again Article describing how to […]

Recommended Articles

Recommended Articles – July 2014

Zebra Puzzle is a very good didactic problem for understanding constraints. Tudor Timisescu, the blog’s author, takes the effort in showing us what problems he encountered while building the constraints in SystemVerilog. Verification Gentleman: Fun and Games with CRV: The Zebra Puzzle If you want to know how to constraint elements of a dynamic array […]