Aurelian Ionel Munteanu

How to Ignore Cross Coverage Bins Using Expressions in SystemVerilog

Lately, I’ve been playing with the coverage features of SystemVerilog. One thing I wanted to do was to filter out some bins from the auto-generated list of cross bins. I searched the Internet for a solution, but only found similar questions with no clear answers. Therefore, I started to work on this problem and came […]

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Recommended Articles – August 2014

A library for upgrading SystemVerilog’s capabilities. It handles file, string manipulation routines and more: Verilab: Library code – svlib Verilab: System Verilog, Batteries included A library for enhancing SystemVerilog types and their pseudo-methods: ClueLogic: CluLib Online Documentation ClueLogic: ClueLib code ClueLogic: Sharing Generic Class Libraries in SystemVerilog Makes Coding Fun Again Article describing how to […]

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Recommended Articles – July 2014

Zebra Puzzle is a very good didactic problem for understanding constraints. Tudor Timisescu, the blog’s author, takes the effort in showing us what problems he encountered while building the constraints in SystemVerilog. Verification Gentleman: Fun and Games with CRV: The Zebra Puzzle If you want to know how to constraint elements of a dynamic array […]

Aurelian Ionel Munteanu

Save Time in Pre-Silicon Functional Verification Using Regression Automation Scripts

We do pre-silicon verification in multiple iterations, each iteration including at least a regression. Regressions consume a great deal of HW resources (e.g. CPU time) and SW resources (e.g. licenses) and… a lot of human effort. This is what usually happens when we run a regression: we aim to reduce the time spent in regression […]