Aurelian Ionel Munteanu

Einsten’s Five House Riddle – e-language Solution

A few weeks ago Sandeep Gor from DigitalVerification launched a challenge for the e-language speakers. The challenge requires solving Einstein’s five house riddle: Image Source Variations of this riddle appear on the internet from time to time. It is sometimes attributed to Albert Einstein and it is claimed that 98% of the people are incapable […]

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Recommended Articles – October 2015

New entry on our list, Jason Yu impressed us with his eloquent and easy to follow style. He shares his opinion on how Verilog constructs should be used: VerilogPro: Verilog twins: case, casez, casex. Which Should I Use? VerilogPro: One-hot State Machine in SystemVerilog – Reverse Case Statement LearnUVMVerification presents the interaction between UVM driver […]

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Recommended Articles – September 2015

SystemVerilog interfaces are rigid constructs that don’t offer the flexibility of a class (e.g. polymorphism). Tudor Timisescu presents a recipe to create flavors of an interface, recipe which avoids turning the interface into a big, monolithic structure: VerificationGentleman: On SystemVerilog Interface Polymorphism and Extendability Did you ever think of functional coverage patterns?Well, our colleague Stefan […]

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Recommended Articles – August 2015

Nicolaj Schweitz has compiled a metric-driven methodology that shall improve the testing capabilities in an Agile environment: NicolajSchweitz: Can metrics improve agile testing? Measure, Analyse, Adjust Rys Sommefeldt writes the story of chip development, a story where customers, engineers, tools, hardware, technologies and financial decisions take the stage: RysSommefeldt: Semiconductors from idea to product UVM […]

Aurelian Ionel Munteanu

Gotcha: Using SystemVerilog Expressions as Array Indices

Using expressions in arrays indices may lead to unexpected behavior. For example: module top; initial begin automatic int array[10] = {0,1,2,3,4,5,6,7,8,9}; automatic bit idx1 = 1; automatic bit[1:0] idx2 = 3; // Is idx1+idx2 equal to 4 ? if (array[idx1+idx2] != array[4]) begin $error($sformatf(“array[%0d] != array[4]”,idx1+idx2)); end end endmodule OUTPUT: Error: array[0] != array[4] In […]

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Recommended Articles – July 2015

Accellera Systems Initiative and IEEE Standards Association announced that UVM1.2 will be delivered as a contribution to the IEEE P1800.2™ standard. Check out Accellera’s press release for more details. UVM is a methodology which creates opportunities. LearnUVMVerification, a new entry on our radar, takes this opportunity and prepares a series of lessons that explore UVM. […]