Marius Cătălin Gherasim

Register Agent: A UVC for Register Access

The register verification process consists of access verification and functional verification. Register access verification ensures that each register can be correctly accessed in any succession of transactions, with no DUT (Design Under Test) freezing, etc. In order to achieve this, a large spectrum of transactions needs to be generated with high reaccess frequencies for the […]

Vlad Mocanu, Tiberiu Petre

C++ Register Modeling Framework

Some time ago we developed a lightweight register modeling framework, amiq_rm, similar with the uvm_reg and vr_ad libraries. We implemented amiq_rm in C++ such that we could seamlessly integrate it with both SystemC and C++-based projects. Here are the main features of amiq_rm: Simple and intuitive API (HTML documentation included) You can group registers into […]