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Gotcha: Using “rand” Modifier for Object Handles is not enough!

SystemVerilog allows rand modifier to be used for object handles and the object will be randomized only if it is not null. The “gotcha” is that, depending on the simulator, no error or warning will be issued if you forget to initialize the randomized object. Here is an example that illustrates the gotcha: class item; […]

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Recommended Articles – February 2015

Although February was a 28 days month the Verification community was more active than on a 31 days month. The random generation strategy could be the root cause of long time required to achieve coverage closure. Claudia provides a use case scenario for evaluating coverage closure in relation to generation strategy: AMIQ Blog: A Coverage […]

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Gotcha: Function Calls in SystemVerilog Constraints

SystemVerilog allows to call functions inside constraints, although, as I found out, it is a sensitive topic. Here is an example: class constraint_container; rand int unsigned a, b, c; function int unsigned get_a(); return a; endfunction function int unsigned value_of(int unsigned value); return value; endfunction constraint a_constraint { a == 5; // I expect “b” […]

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Gotcha: SystemVerilog’s post_randomize() is Called Top-Down Not Bottom-Up

SystemVerilog classes contain the pre-defined function post_randomize(), which is automatically called at the end of the randomization. One can override this function to do extra processing after randomization. In SystemVerilog post_randomize() is called top-down and not bottom-up! The top-down call of post_randomize() is counter-intuitive, especially for those of you in love with e-Language, and it […]