- Horia-Răzvan Enescu
- Verification Engineer
How to Avoid Parameter Creep for Parameterizable Agents and Interfaces
- November 13th, 2017
- 6 Comments
For configurable protocols, it is useful to have a single agent which can adapt to any protocol configuration. If the agent and the interface are parameterized, having a large number of configuration options will require using many parameters. This can quickly lead to parameter creep: explicitly specifying and propagating all the parameters throughout the environment. […]
- Horia-Răzvan Enescu
- Verification Engineer
How to Unpack Data Using the SystemVerilog Streaming Operators (>>, <<)
- June 23rd, 2017
- 4 Comments
In this post I show how to use the streaming operators to unpack data into variables or data structures in SystemVerilog. This is the second part of a 3-post series on data packing/unpacking operations and the natural follow-up to the first part that focuses on packing data using streaming operators. The unpacking operation is the […]
- Horia-Răzvan Enescu
- Verification Engineer
How to Pack Data Using the SystemVerilog Streaming Operators (>>, <<)
- May 29th, 2017
- 7 Comments
The verification of digital circuits requires dealing with bits and bytes. It is not a trivial thing to pack or unpack bits, bytes, half words, words or user defined data structures. This post is the first in a series of tutorials about packing and unpacking in SystemVerilog. The article’s sections are: Introduction 1. Pack bytes […]
- Stefan Birman
- Verification Engineer
How To Reduce the Number of VIP Instances using Accessor Classes
- May 9th, 2017
- No Comments
In this post I demonstrate how to use parameterization and accessor classes in order to reduce a variable number of VIP instances to a single VIP instance. The implementation I describe might improve the overall performance of the verification environment by reducing the number of threads and the amount of maintenance required (e.g. fewer instances, […]
- Horia-Răzvan Enescu
- Verification Engineer
How to Implement Flexible Coverage Definitions (Part 3)
- June 10th, 2016
- 2 Comments
In the final part of this 3-post series (Part 1, Part 2), I will show a way of covering enum transitions and conditionally ignoring transitions to and from certain enum values. For example, in the case of a CPU’s instruction set, you want to make sure that all possible combinations of two consecutive instructions are […]
- Horia-Răzvan Enescu
- Verification Engineer
How to Implement Flexible Coverage Definitions (Part 2)
- May 19th, 2016
- No Comments
In part 1 of this 3-post series, I presented a way of defining flexible coverage definitions in SystemVerilog using the with clause. In this second post, I will show a way of achieving the same flexibility for transition coverage. As SystemVerilog’s grammar doesn’t allow us to use the with clause for defining transition bins, we […]
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