- Stefan Birman
- Verification Engineer
How To Protect FIFOs Against Overflow – Part 2
- August 27th, 2018
- No Comments
This post is a follow-up of the How To Protect FIFOs Against Overflow – Part 1 and it details the second proposed solution. The complete implementation presented in this post can be downloaded from GitHub. That being said, let’s go through the implementation, step-by-step. Step 1. Define enumeration items that identify the two FIFOs typedef […]
- Stefan Birman
- Verification Engineer
How To Protect FIFOs Against Overflow – Part 1
- July 25th, 2018
- 2 Comments
Systems containing FIFOs face verification engineers with a “classic” black-box verification problem: how to protect FIFOs against overflow in order to avoid unpredictable loss of packets. The difficulty in solving this problem comes from the lack of visibility into DUT’s internal states, which means the solution should count only on the events/packets driven/monitored on the […]
- Horia-Răzvan Enescu
- Verification Engineer
How to Avoid Parameter Creep for Parameterizable Agents and Interfaces
- November 13th, 2017
- 6 Comments
For configurable protocols, it is useful to have a single agent which can adapt to any protocol configuration. If the agent and the interface are parameterized, having a large number of configuration options will require using many parameters. This can quickly lead to parameter creep: explicitly specifying and propagating all the parameters throughout the environment. […]
- Horia-Răzvan Enescu
- Verification Engineer
How to Unpack Data Using the SystemVerilog Streaming Operators (>>, <<)
- June 23rd, 2017
- 4 Comments
In this post I show how to use the streaming operators to unpack data into variables or data structures in SystemVerilog. This is the second part of a 3-post series on data packing/unpacking operations and the natural follow-up to the first part that focuses on packing data using streaming operators. The unpacking operation is the […]
- Horia-Răzvan Enescu
- Verification Engineer
How to Pack Data Using the SystemVerilog Streaming Operators (>>, <<)
- May 29th, 2017
- 8 Comments
The verification of digital circuits requires dealing with bits and bytes. It is not a trivial thing to pack or unpack bits, bytes, half words, words or user defined data structures. This post is the first in a series of tutorials about packing and unpacking in SystemVerilog. The article’s sections are: Introduction 1. Pack bytes […]
- Stefan Birman
- Verification Engineer
How To Reduce the Number of VIP Instances using Accessor Classes
- May 9th, 2017
- No Comments
In this post I demonstrate how to use parameterization and accessor classes in order to reduce a variable number of VIP instances to a single VIP instance. The implementation I describe might improve the overall performance of the verification environment by reducing the number of threads and the amount of maintenance required (e.g. fewer instances, […]
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