- Florin Oancea
- Verification Engineer
How to Match Strings in SystemVerilog Using Regular Expressions
- September 11th, 2020
- 1 Comment
Recently, I needed to filter out some instance paths from my UVM testbench hierarchy. I discovered that this can be done using regular expressions and that UVM already has a function called uvm_pkg::uvm_re_match(), which is a DPI-C function that makes use of the POSIX function regexec() to perform a string match. The uvm_re_match function will […]
- Cristian Bob
- Verification Engineer
How to Connect e-Language with Python
- May 17th, 2019
- No Comments
This post is an addition to the previous post How to connect SystemVerilog with Python. The principles of connecting e-Language with Python are similar to those presented in the aforementioned post. Table of contents Create the e-Language-to-C Interface Client Layer Code Changes Create the Top Modules How To Run the Example Create the e-Language-to-C Interface […]
- DPI-C , e-Language , how to , Python
- Cristian Bob
- Verification Engineer
How to Connect SystemVerilog with Python
- March 22nd, 2019
- 11 Comments
Verification of a digital design often requires an interaction between several language domains (SystemVerilog and C, SystemVerilog and Python, SystemVerilog and e-language, etc.). This article shows you how to set up a connection between SystemVerilog and Python. SystemVerilog is not able to communicate directly with Python. Instead, the SV code first needs to talk to […]
- DPI-C , how to , Python , SystemVerilog
- Sergiu Duda
- Verification Engineer
How to Implement a Convolutional Neural Network Using High Level Synthesis
- December 14th, 2018
- 29 Comments
Introduction Deep Learning has taken the world by storm and now has applications in almost every field, from image and speech recognition to medical software, from data analysis to the fine arts. Even though the idea of Deep Learning is not new and the basic principle is pretty straightforward, only recently has it grown in […]
- deep learning , FPGA , HLS , how to
- Stefan Birman
- Verification Engineer
How To Protect FIFOs Against Overflow – Part 2
- August 27th, 2018
- No Comments
This post is a follow-up of the How To Protect FIFOs Against Overflow – Part 1 and it details the second proposed solution. The complete implementation presented in this post can be downloaded from GitHub. That being said, let’s go through the implementation, step-by-step. Step 1. Define enumeration items that identify the two FIFOs typedef […]
- Stefan Birman
- Verification Engineer
How To Protect FIFOs Against Overflow – Part 1
- July 25th, 2018
- 2 Comments
Systems containing FIFOs face verification engineers with a “classic” black-box verification problem: how to protect FIFOs against overflow in order to avoid unpredictable loss of packets. The difficulty in solving this problem comes from the lack of visibility into DUT’s internal states, which means the solution should count only on the events/packets driven/monitored on the […]
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