- Cristian Bob
- Verification Engineer
How to Connect SystemVerilog with Python
- March 22nd, 2019
- 8 Comments
Verification of a digital design often requires an interaction between several language domains (SystemVerilog and C, SystemVerilog and Python, SystemVerilog and e-language, etc.). This article shows you how to set up a connection between SystemVerilog and Python. SystemVerilog is not able to communicate directly with Python. Instead, the SV code first needs to talk to […]
- Sergiu Duda
- Verification Engineer
How to Implement a Convolutional Neural Network Using High Level Synthesis
- December 14th, 2018
- 2 Comments
Introduction Deep Learning has taken the world by storm and now has applications in almost every field, from image and speech recognition to medical software, from data analysis to the fine arts. Even though the idea of Deep Learning is not new and the basic principle is pretty straightforward, only recently has it grown in […]
- deep learning , FPGA , HLS , how to
- Stefan Birman
- Verification Engineer
How To Protect FIFOs Against Overflow – Part 2
- August 27th, 2018
- No Comments
This post is a follow-up of the How To Protect FIFOs Against Overflow – Part 1 and it details the second proposed solution. The complete implementation presented in this post can be downloaded from GitHub. That being said, let’s go through the implementation, step-by-step. Step 1. Define enumeration items that identify the two FIFOs typedef […]
- Stefan Birman
- Verification Engineer
How To Protect FIFOs Against Overflow – Part 1
- July 25th, 2018
- 2 Comments
Systems containing FIFOs face verification engineers with a “classic” black-box verification problem: how to protect FIFOs against overflow in order to avoid unpredictable loss of packets. The difficulty in solving this problem comes from the lack of visibility into DUT’s internal states, which means the solution should count only on the events/packets driven/monitored on the […]
- Horia-Răzvan Enescu
- Verification Engineer
How to Avoid Parameter Creep for Parameterizable Agents and Interfaces
- November 13th, 2017
- 6 Comments
For configurable protocols, it is useful to have a single agent which can adapt to any protocol configuration. If the agent and the interface are parameterized, having a large number of configuration options will require using many parameters. This can quickly lead to parameter creep: explicitly specifying and propagating all the parameters throughout the environment. […]
- Horia-Răzvan Enescu
- Verification Engineer
How to Unpack Data Using the SystemVerilog Streaming Operators (>>, <<)
- June 23rd, 2017
- 5 Comments
In this post I show how to use the streaming operators to unpack data into variables or data structures in SystemVerilog. This is the second part of a 3-post series on data packing/unpacking operations and the natural follow-up to the first part that focuses on packing data using streaming operators. The unpacking operation is the […]
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