Horia-Răzvan Enescu

How To: Alternative Ways to Implement Bitwise Coverage

In a previous post, Stefan provided implementations for several bitwise coverage patterns. In this post I will show an alternative way of implementing a couple of them, avoiding the usage of loops to iterate through all bits. Walking 1 and Walking 0 Coverage covergroup walking1_cg with function sample(bit [WIDTH-1:0] x); walking1_cp: coverpoint ($clog2(x) iff ($onehot(x)) […]

Cristiana Stan

CoverageLens 2.0 Release

Coverage Lens (CL) is a C++ utility that checks if a specified set of RTL code coverage items (e.g. statement, condition etc.) is covered by querying an UCIS compliant coverage database. The main functionality is described in the How To Automate Code Coverage analysis with Coverage Lens article. CoverageLens 2.0 release includes support for functional […]

Teo Vasilache

How to Export Functional Coverage from SystemC to SystemVerilog

This post presents a way to collect functional coverage from SystemC models using SystemVerilog covergroups and UVM-ML/UVM-Connect. Functional coverage is not standardized yet in SystemC, but there is a workaround for the case of mixed-language(SystemC/SystemVerilog) verification environments. This workaround makes use of covergroups from SystemVerilog and TLM transactions from SystemC and SystemVerilog. When a sampling […]

Stefan Birman

Functional Coverage Patterns: The Counter

This post explains the functional verification of counters and it is part of a series of posts exploring functional coverage patterns. The first post in the series was Functional Coverage Patterns: Bitwise Coverage. Table of contents What is a Counter? Counter Verification Regarding Synchronicity Reset Value Coverage Clear Value Coverage Overflow and Underflow Policy Coverage […]

Recommended Articles

Recommended Articles – June 2016

Implementing coverage in SystemVerilog can become a challenging task. Horia presents the last article from a series of 3, on how to implement flexible coverage. AMIQ: How to Implement Flexible Coverage Definitions (Part 3) Henry Chan presents a high level overview of the uvm_reg package: SemiEngineering: UVM Register Layer: The Structure Here it is a […]

Horia-Răzvan Enescu

How to Implement Flexible Coverage Definitions (Part 3)

In the final part of this 3-post series (Part 1, Part 2), I will show a way of covering enum transitions and conditionally ignoring transitions to and from certain enum values. For example, in the case of a CPU’s instruction set, you want to make sure that all possible combinations of two consecutive instructions are […]