Recommended Articles

Recommended Articles – October 2020

AMIQ has released a new UVC that facilitates register accesses. It is called Register Agent: Register Agent: A UVC for Register Access. Manish from Learn UVM Verification explains why we need a UVM Register Abstraction Layer: Why UVM RAL is needed?. Cadence released a new feature that allows you to integrate Python code into e-language. […]

Cristian Bob

How to Connect e-Language with Python

This post is an addition to the previous post How to connect SystemVerilog with Python. The principles of connecting e-Language with Python are similar to those presented in the aforementioned post. Table of contents Create the e-Language-to-C Interface Client Layer Code Changes Create the Top Modules How To Run the Example Create the e-Language-to-C Interface […]

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Recommended Articles – March 2017

Using SystemVerilog along UVM methodology can be a difficult road for a newbie. Mentor together with Sandeep Nasa and Shankar Arora from Logic Fruit Technologies, have compiled a list of UVM tips&tricks that help you avoid some of the language traps and might improve performance. Read more on UVM Tips and Tricks Cadence has added […]

Recommended Articles

Recommended Articles – February 2017

Solving sudoku is fun. Solving sudoku using SystemVerilog is both fun and instructive. In a 2015 article, Keisuke Shimizu from ClueLogic, provided a SystemVerilog solution for solving sudoku. In the 2017 version he provides a different solution that makes use of “unique” SystemVerilog keyword. Read all about it here: Hidden Gems of SystemVerilog – 4. […]

Recommended Articles

Recommended Articles – December 2016

Often, it happens that the information about a Design Under Test (DUT) or about its verification is being organized in the form of a table like structure (configurations, registers, operation modes, traffic types, etc.). Imagine if you could automatically create bits of code from an Excel table. How awesome is that! E-language is now able […]

Recommended Articles

Recommended Articles – October 2016

New entry on our list: FPGASite is a nice resource for FPGA/VHDL enthusiasts. Claudio Avi Cham, the owner of the website, shows how to implement an arbiter in VHDL: FPGASite: VHDL Arbiter Part 1, Part 2, Part 3 What does a Functional Verification Engineer (FVE) do and how can you become an FVE? Stefan Birman, […]