Ioana Catalina Cristea

OFC – Open-source Framework for Co-emulation using PYNQ

This article is a summary of the paper “Open-Source Framework for Co-Emulation using PYNQ” which was presented at the DVCon U.S. 2021 Conference. Table of Contents Resources What is co-emulation? What is OFC? Basic Concepts Layer 1: Host – Verification Environment Layer 2: Pynq – Processing System Layer 3: Pynq – Programmable Logic User Integration […]

Aurelian Ionel Munteanu

SystemVerilog and SVA Cheatsheet

Have you ever missed a SystemVerilog or an SVA cheatsheet? I surely did and so did my colleagues. As programmers, many times we want just a quick preview of a specific language construct and not to read the full manual. Starting today, instead of browsing through hundreds of pages of the SystemVerilog LRM you can […]

Florin Oancea

How to Match Strings in SystemVerilog Using Regular Expressions

Recently, I needed to filter out some instance paths from my UVM testbench hierarchy. I discovered that this can be done using regular expressions and that UVM already has a function called uvm_pkg::uvm_re_match(), which is a DPI-C function that makes use of the POSIX function regexec() to perform a string match. The uvm_re_match function will […]

Ioana Catalina Cristea

Non-Blocking Socket Communication in SystemVerilog Using DPI-C

As discussed in a previous article (How to Connect SystemVerilog with Python), functional verification may require an interaction between the testbench and components written in various programming languages. The above-mentioned post describes a method for connecting SystemVerilog with Python that assumes a one-to-one relationship between the sent and received packets. This implies that the communication […]

Cristian Bob

How to Connect SystemVerilog with Python

Verification of a digital design often requires an interaction between several language domains (SystemVerilog and C, SystemVerilog and Python, SystemVerilog and e-language, etc.). This article shows you how to set up a connection between SystemVerilog and Python. SystemVerilog is not able to communicate directly with Python. Instead, the SV code first needs to talk to […]

Aurelian Ionel Munteanu

How to Call C-functions from SystemVerilog Using DPI-C

Recently I played a bit with SystemVerilog and DPI-C and I thought of sharing the experience with you. This post shows data types mappings from SystemVerilog to C and how to call C-functions from SV. I also provide a simple SV/C application to facilitate understanding of data types mappings. Data Mappings When SystemVerilog interacts with […]