Recommended Articles

Recommended Articles – March 2018

Team Specman casts a new light on how to make the verification environment sensitive to reset. You can read about that in Temporals, Reset, and Test Phases Cadence has compiled some short guidelines which can optimize your SystemVerilog code. Take a look at them and check which one is already on your list and which […]

Horia-Răzvan Enescu

How To: Alternative Ways to Implement Bitwise Coverage

In a previous post, Stefan provided implementations for several bitwise coverage patterns. In this post I will show an alternative way of implementing a couple of them, avoiding the usage of loops to iterate through all bits. Walking 1 and Walking 0 Coverage covergroup walking1_cg with function sample(bit [WIDTH-1:0] x); walking1_cp: coverpoint ($clog2(x) iff ($onehot(x)) […]

Horia-Răzvan Enescu

How to Avoid Parameter Creep for Parameterizable Agents and Interfaces

For configurable protocols, it is useful to have a single agent which can adapt to any protocol configuration. If the agent and the interface are parameterized, having a large number of configuration options will require using many parameters. This can quickly lead to parameter creep: explicitly specifying and propagating all the parameters throughout the environment. […]

Stefan Birman

How To Customize UVM Sequencer’s Arbitration Policy

This post shows how you can implement a custom sequencer arbitration policy in UVM. The example considers a sequence that contains a field called seq_type: typedef enum {MASTER_SEQ, REQ_SEQ, CNFRM_SEQ, ACK_SEQ, REDO_SEQ, DATA_SEQ } ex_seq_type_t; class ex_base_sequence extends uvm_sequence#(ex_sequence_item); ex_seq_type_t seq_type; // this field is used by the arbitration scheme …….. endclass The arbitration policy […]

Teo Vasilache

How to Align SystemVerilog-to-SystemC TLM Transactions Definitions

This post presents a method to align definitions of the objects defined in SystemVerilog and SystemC. An object from SystemVerilog is aligned with an object in SystemC if they both have the same fields with same data types. Verification projects that use both SystemVerilog and SystemC make use of TLM transactions to exchange data between […]

Teo Vasilache

How to Export Functional Coverage from SystemC to SystemVerilog

This post presents a way to collect functional coverage from SystemC models using SystemVerilog covergroups and UVM-ML/UVM-Connect. Functional coverage is not standardized yet in SystemC, but there is a workaround for the case of mixed-language(SystemC/SystemVerilog) verification environments. This workaround makes use of covergroups from SystemVerilog and TLM transactions from SystemC and SystemVerilog. When a sampling […]