- Stefan Birman
- Verification Engineer
Highlights of DVCon EU 2018
- November 20th, 2018
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This post presents some of the highlights of the technical program AMIQ consultants enjoyed attending at DVCon Europe 2018 (24-25 October, Munich). Hot Topics It is quite hard choosing a “hottest” topic, but we did notice that PSS- and SystemC-related papers/tutorials engaged a lot of engineers in discussions. SystemC, Virtual Platforms, System Modeling […]
- Dragos Dospinescu
- Verification Engineer
FC4SC 2.1.1 Release is Available
- November 15th, 2018
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Amiq is pleased to announce the release of the FC4SC 2.1.1! You can read more about the FC4SC library and first release in this blog post. Download Change Log Roadmap Download You can download the FC4SC library from GitHub. For getting up to speed you can read our previous post, download FC4SC’s User Guide or […]
- Teo Vasilache
- Verification Engineer
C++ Implementation of Functional Coverage for SystemC
- February 22nd, 2018
- 6 Comments
We release Functional Coverage for SystemC (FC4SC) library which provides mechanisms for functional coverage definition, collection and reporting. FC4SC is a header-only, C++2011-based library, that can be integrated with C++ applications, including SystemC models. It’s primary use case is to measure the level of exercise of SystemC models, basically to measure how many of model’s […]
- Teo Vasilache
- Verification Engineer
How to Align SystemVerilog-to-SystemC TLM Transactions Definitions
- September 8th, 2017
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This post presents a method to align definitions of the objects defined in SystemVerilog and SystemC. An object from SystemVerilog is aligned with an object in SystemC if they both have the same fields with same data types. Verification projects that use both SystemVerilog and SystemC make use of TLM transactions to exchange data between […]
- Aurelian Ionel Munteanu
- Verification Engineer
Recommended Articles – August 2017
- August 30th, 2017
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New entry on our list FPGA4Student is a website dedicated to provide a lot of source code for various FPGA needs. It’s a good resource for learning how to code in Verilog or VHDL. Here is a comparison between Verilog and VHDL: Explain by Examples. Jason Yu from VerilogPro is set to compare implementation of […]
- Teo Vasilache
- Verification Engineer
How to Export Functional Coverage from SystemC to SystemVerilog
- August 18th, 2017
- No Comments
This post presents a way to collect functional coverage from SystemC models using SystemVerilog covergroups and UVM-ML/UVM-Connect. Functional coverage is not standardized yet in SystemC, but there is a workaround for the case of mixed-language(SystemC/SystemVerilog) verification environments. This workaround makes use of covergroups from SystemVerilog and TLM transactions from SystemC and SystemVerilog. When a sampling […]
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