- Dragos Dospinescu
- Verification Engineer
AMIQ Consulting Contributes C++ Coverage Library to Accellera
- December 10th, 2019
- No Comments
We have posted before about the Functional Coverage for SystemC (FC4SC) library that we developed and made available to the semiconductor industry. We are pleased to report that the Accellera Systems Initiative standards organization has accepted our donation of FC4SC for use by their SystemC Verification Working Group. Since we released FC4SC as open source, […]
- Stefan Birman
- Verification Engineer
Highlights of DVCon EU 2018
- November 20th, 2018
- No Comments
This post presents some of the highlights of the technical program AMIQ consultants enjoyed attending at DVCon Europe 2018 (24-25 October, Munich). Hot Topics It is quite hard choosing a “hottest” topic, but we did notice that PSS- and SystemC-related papers/tutorials engaged a lot of engineers in discussions. SystemC, Virtual Platforms, System Modeling […]
- Dragos Dospinescu
- Verification Engineer
FC4SC 2.1.1 Release is Available
- November 15th, 2018
- 2 Comments
Amiq is pleased to announce the release of the FC4SC 2.1.1! You can read more about the FC4SC library and first release in this blog post. Download Change Log Roadmap Download You can download the FC4SC library from GitHub. For getting up to speed you can read our previous post, download FC4SC’s User Guide or […]
- C++ , FC4SC , functional coverage , SystemC
- Teo Vasilache
- Verification Engineer
C++ Implementation of Functional Coverage for SystemC
- February 22nd, 2018
- 6 Comments
We release Functional Coverage for SystemC (FC4SC) library which provides mechanisms for functional coverage definition, collection and reporting. FC4SC is a header-only, C++2011-based library, that can be integrated with C++ applications, including SystemC models. It’s primary use case is to measure the level of exercise of SystemC models, basically to measure how many of model’s […]
- CPP , FC4SC , functional coverage , GitHub , SystemC , utility library
- Teo Vasilache
- Verification Engineer
How to Align SystemVerilog-to-SystemC TLM Transactions Definitions
- September 8th, 2017
- No Comments
This post presents a method to align definitions of the objects defined in SystemVerilog and SystemC. An object from SystemVerilog is aligned with an object in SystemC if they both have the same fields with same data types. Verification projects that use both SystemVerilog and SystemC make use of TLM transactions to exchange data between […]
- Aurelian Ionel Munteanu
- Verification Engineer
Recommended Articles – August 2017
- August 30th, 2017
- No Comments
New entry on our list FPGA4Student is a website dedicated to provide a lot of source code for various FPGA needs. It’s a good resource for learning how to code in Verilog or VHDL. Here is a comparison between Verilog and VHDL: Explain by Examples. Jason Yu from VerilogPro is set to compare implementation of […]
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