- Teo Vasilache
- Verification Engineer
C++ Implementation of Functional Coverage for SystemC
- February 22nd, 2018
- 4 Comments
We release Functional Coverage for SystemC (FC4SC) library which provides mechanisms for functional coverage definition, collection and reporting. FC4SC is a header-only, C++2011-based library, that can be integrated with C++ applications, including SystemC models. It’s primary use case is to measure the level of exercise of SystemC models, basically to measure how many of model’s […]
- Teo Vasilache
- Verification Engineer
How to Align SystemVerilog-to-SystemC TLM Transactions Definitions
- September 8th, 2017
- No Comments
This post presents a method to align definitions of the objects defined in SystemVerilog and SystemC. An object from SystemVerilog is aligned with an object in SystemC if they both have the same fields with same data types. Verification projects that use both SystemVerilog and SystemC make use of TLM transactions to exchange data between […]
- Aurelian Ionel Munteanu
- Verification Engineer
Recommended Articles – August 2017
- August 30th, 2017
- No Comments
New entry on our list FPGA4Student is a website dedicated to provide a lot of source code for various FPGA needs. It’s a good resource for learning how to code in Verilog or VHDL. Here is a comparison between Verilog and VHDL: Explain by Examples. Jason Yu from VerilogPro is set to compare implementation of […]
- Teo Vasilache
- Verification Engineer
How to Export Functional Coverage from SystemC to SystemVerilog
- August 18th, 2017
- No Comments
This post presents a way to collect functional coverage from SystemC models using SystemVerilog covergroups and UVM-ML/UVM-Connect. Functional coverage is not standardized yet in SystemC, but there is a workaround for the case of mixed-language(SystemC/SystemVerilog) verification environments. This workaround makes use of covergroups from SystemVerilog and TLM transactions from SystemC and SystemVerilog. When a sampling […]
- Vlad Mocanu, Tiberiu Petre
- Verification Engineers
C++ Register Modeling Framework
- December 9th, 2015
- No Comments
Some time ago we developed a lightweight register modeling framework, amiq_rm, similar with the uvm_reg and vr_ad libraries. We implemented amiq_rm in C++ such that we could seamlessly integrate it with both SystemC and C++-based projects. Here are the main features of amiq_rm: Simple and intuitive API (HTML documentation included) You can group registers into […]
- CPP , GitHub , register model , SystemC
- Stefan Birman
- Verification Engineer
A Conference to Attend: Forum on Specification and Design Languages
- October 12th, 2015
- No Comments
Between 14-15th of September I attended the Forum on Specification and Design Languages(FDL) in Barcelona, a niche conference that covers subjects such as modeling languages, system modelling (digital, analog and mixed signal), power and performance modelling, high level synthesis, high performance computing and parallel programming. There were 2 keynote presentations, 7 lectures and 10 panelists […]
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