Recommended Articles

Recommended Articles – October 2020

AMIQ has released a new UVC that facilitates register accesses. It is called Register Agent: Register Agent: A UVC for Register Access. Manish from Learn UVM Verification explains why we need a UVM Register Abstraction Layer: Why UVM RAL is needed?. Cadence released a new feature that allows you to integrate Python code into e-language. […]

Ioana Catalina Cristea

Non-Blocking Socket Communication in SystemVerilog Using DPI-C

As discussed in a previous article (How to Connect SystemVerilog with Python), functional verification may require an interaction between the testbench and components written in various programming languages. The above-mentioned post describes a method for connecting SystemVerilog with Python that assumes a one-to-one relationship between the sent and received packets. This implies that the communication […]

Cristian Bob

How to Connect e-Language with Python

This post is an addition to the previous post How to connect SystemVerilog with Python. The principles of connecting e-Language with Python are similar to those presented in the aforementioned post. Table of contents Create the e-Language-to-C Interface Client Layer Code Changes Create the Top Modules How To Run the Example Create the e-Language-to-C Interface […]

Cristian Bob

How to Connect SystemVerilog with Python

Verification of a digital design often requires an interaction between several language domains (SystemVerilog and C, SystemVerilog and Python, SystemVerilog and e-language, etc.). This article shows you how to set up a connection between SystemVerilog and Python. SystemVerilog is not able to communicate directly with Python. Instead, the SV code first needs to talk to […]