- Ioana Catalina Cristea
- Verification Engineer
OFC – Open-source Framework for Co-emulation using PYNQ
- March 5th, 2021
- 2 Comments
This article is a summary of the paper “Open-Source Framework for Co-Emulation using PYNQ” which was presented at the DVCon U.S. 2021 Conference. Table of Contents Resources What is co-emulation? What is OFC? Basic Concepts Layer 1: Host – Verification Environment Layer 2: Pynq – Processing System Layer 3: Pynq – Programmable Logic User Integration […]
- amiq_ofc , Co-emulation , FPGA , OFC , Python , SystemVerilog
- Sergiu Duda
- Verification Engineer
How to Implement a Convolutional Neural Network Using High Level Synthesis
- December 14th, 2018
- 38 Comments
Introduction Deep Learning has taken the world by storm and now has applications in almost every field, from image and speech recognition to medical software, from data analysis to the fine arts. Even though the idea of Deep Learning is not new and the basic principle is pretty straightforward, only recently has it grown in […]
- deep learning , FPGA , HLS , how to
- Aurelian Ionel Munteanu
- Verification Engineer
Recommended Articles – February 2016
- March 16th, 2016
- 4 Comments
Anders Nordstrom has written one of the best articles I’ve read about the effects of over-constraining properties in formal verification. The author describes what’s safe to do and what’s not safe to do when using formal methodologies: EDN: Anders Nordstrom: Don’t over-constrain in formal property verification (FPV) flows High speed serial communication protocols like Ethernet, […]
- algorithms , debug , e-Language , formal verification , FPGA , recommended articles , UVM
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