Recommended Articles

Recommended Articles – September 2018

In case of e-language it is the aspect oriented-nature of the language itself that helps cutting down the compile and simulation rerun time. You can read more about dynamic load or just-in-time patching: Adding a Patch Just in Time!. I always try to find ways of shortening the time it takes to wait for various […]

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Recommended Articles – July 2018

AMIQ Education Program saga continues…. This years’ summer school received more attention from the students according to Stefan’s feedback: Digital Circuits Simulation and Verification Summer School. FIFOs are encountered in many digital designs and the verification of such designs comes with specific challenges, one of them being to protect the FIFOs against overflow. You can […]

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Recommended Articles – June 2018

We present to you the SystemVerilog and VHDL Grammars in HTML format. The grammars represent the BNF (Backus-Naur Form) notation in an HTML format, with hyperlinks, anchors and tooltips. You can also download them from the GitHub repository. John Neil, from AgileSOC, continues his reflection on how verification engineers should think about their testbench code: […]

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Recommended Articles – May 2018

Here is an interesting article discussing if any FPGA implementation contains an internal tri-state bus or not: FPGA internal tri-state buses I’m not a fan of long articles, but the subject of the following ones is of real interest for verification engineers. It is a transcript of a discussion between representatives of major EDA companies […]

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Recommended Articles – April 2018

This month, Neil Johnson (AgileSOC) has challenged the verification community in an attempt to define a scope for the new Portable Stimulus Standard (PSS) and a place among the other existing verification techniques. He presents his view in a series of three articles. One of the articles presents each verification technique and its scope. In […]

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Recommended Articles – March 2018

Team Specman casts a new light on how to make the verification environment sensitive to reset. You can read about that in Temporals, Reset, and Test Phases Cadence has compiled some short guidelines which can optimize your SystemVerilog code. Take a look at them and check which one is already on your list and which […]