Recommended Articles

Recommended Articles – August 2018

In his article about how to avoid FIFO overflows, Stefan promised a second solution. Here is part II of the article presenting the solution which makes use of uvm constructs. Neil from AgileSOC continues to simplify the SVAUnit framework. He makes use of his new mocking framework in order to decouple the driver from the […]

Recommended Articles

Recommended Articles – October 2017

Cristian from CFSVision continues the SystemC series with two new tutorials addressing Time, Events and Processes and Mutex, Semaphores and FIFOs. Stefan from Amiq shows how to create a custom sequencer arbitration policy in UVM. In AMIQ Resources page you can find the contents of AMIQ’s bookshelf, papers and the list of blogs we periodically […]

Recommended Articles

Recommended Articles – July 2017

 Tudor (Verification Gentleman) continues his series of articles on unit testing with a case study on Testing SVA Properties and Sequences.  Ben Cohen (SystemVerilog.us) goes into details on how tasks and threads are used inside System Verilog Assertions. The Understanding the SVA Engine + Simple alternate solutions article also includes an SVA example that is […]

Daniel Ciupitu

To be or not to be a Verification Engineer

A verification engineer builds verification environments used to hunt for hardware design flaws and prove a product will operate as expected. But what does that really mean? Do you have the skills to do this job? And should someone even consider doing it? This post is a follow-up to Stefan’s job description of a verification […]

Daniel Ciupitu

Coverage Aware Generation using e Language Normal Distribution Constraints

When defining coverage items we need to make a trade-off between the number of coverage buckets, their size and the simulation time required to get them covered. From our experience the solution is to generate items being aware of how they will be covered. For example if the coverage item has power-of-2 buckets, the generated […]