- Florin Oancea
- Verification Engineer
How to Match Strings in SystemVerilog Using Regular Expressions
- September 11th, 2020
- 1 Comment
Recently, I needed to filter out some instance paths from my UVM testbench hierarchy. I discovered that this can be done using regular expressions and that UVM already has a function called uvm_pkg::uvm_re_match(), which is a DPI-C function that makes use of the POSIX function regexec() to perform a string match. The uvm_re_match function will […]
- Florin Oancea
- Verification Engineer
Migrating to UVM 1.2
- June 6th, 2014
- 3 Comments
A couple of days ago I watched a presentation on UVM 1.2 by Tom Fitzpatrick of Mentor Graphics posted on Verification Academy, and I thought to give it a try and port one of our verification environments based on UVM 1.1d. Here is what my experience has been, originally posted on Accellera. 1. Download UVM […]
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