- Ioana Catalina Cristea
- Verification Engineer
OFC – Open-source Framework for Co-emulation using PYNQ
- March 5th, 2021
- 2 Comments
This article is a summary of the paper “Open-Source Framework for Co-Emulation using PYNQ” which was presented at the DVCon U.S. 2021 Conference. Table of Contents Resources What is co-emulation? What is OFC? Basic Concepts Layer 1: Host – Verification Environment Layer 2: Pynq – Processing System Layer 3: Pynq – Programmable Logic User Integration […]
- amiq_ofc , Co-emulation , FPGA , OFC , Python , SystemVerilog
- Ioana Catalina Cristea
- Verification Engineer
Non-Blocking Socket Communication in SystemVerilog Using DPI-C
- August 14th, 2020
- No Comments
As discussed in a previous article (How to Connect SystemVerilog with Python), functional verification may require an interaction between the testbench and components written in various programming languages. The above-mentioned post describes a method for connecting SystemVerilog with Python that assumes a one-to-one relationship between the sent and received packets. This implies that the communication […]
- DPI-C , Python , SystemVerilog
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