Horia-Răzvan Enescu

How To: Alternative Ways to Implement Bitwise Coverage

In a previous post, Stefan provided implementations for several bitwise coverage patterns. In this post I will show an alternative way of implementing a couple of them, avoiding the usage of loops to iterate through all bits. Walking 1 and Walking 0 Coverage covergroup walking1_cg with function sample(bit [WIDTH-1:0] x); walking1_cp: coverpoint ($clog2(x) iff ($onehot(x)) […]

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How to Avoid Parameter Creep for Parameterizable Agents and Interfaces

For configurable protocols, it is useful to have a single agent which can adapt to any protocol configuration. If the agent and the interface are parameterized, having a large number of configuration options will require using many parameters. This can quickly lead to parameter creep: explicitly specifying and propagating all the parameters throughout the environment. […]

Horia-Răzvan Enescu

How to Unpack Data Using the SystemVerilog Streaming Operators (>>, <<)

In this post I show how to use the streaming operators to unpack data into variables or data structures in SystemVerilog. This is the second part of a 3-post series on data packing/unpacking operations and the natural follow-up to the first part that focuses on packing data using streaming operators. The unpacking operation is the […]

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How to Pack Data Using the SystemVerilog Streaming Operators (>>, <<)

The verification of digital circuits requires dealing with bits and bytes. It is not a trivial thing to pack or unpack bits, bytes, half words, words or user defined data structures. This post is the first in a series of tutorials about packing and unpacking in SystemVerilog. The article’s sections are: Introduction 1. Pack bytes […]

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How to Implement Flexible Coverage Definitions (Part 3)

In the final part of this 3-post series (Part 1, Part 2), I will show a way of covering enum transitions and conditionally ignoring transitions to and from certain enum values. For example, in the case of a CPU’s instruction set, you want to make sure that all possible combinations of two consecutive instructions are […]

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How to Implement Flexible Coverage Definitions (Part 2)

In part 1 of this 3-post series, I presented a way of defining flexible coverage definitions in SystemVerilog using the with clause. In this second post, I will show a way of achieving the same flexibility for transition coverage. As SystemVerilog’s grammar doesn’t allow us to use the with clause for defining transition bins, we […]