Andra Socianu, Daniel Ciupitu

How to Connect SystemVerilog with Octave

When we must verify a highly computational RTL, we may deal with complicated mathematical functions and algorithms. Implementing and debugging an RTL model can be tricky and time consuming. In such cases modeling using Octave/Matlab, C/C++ or SystemC can be a good alternative. In this article we present a “Hello world!” example to illustrate how […]