Teo Vasilache

How to Align SystemVerilog-to-SystemC TLM Transactions Definitions

This post presents a method to align definitions of the objects defined in SystemVerilog and SystemC. An object from SystemVerilog is aligned with an object in SystemC if they both have the same fields with same data types. Verification projects that use both SystemVerilog and SystemC make use of TLM transactions to exchange data between […]

Recommended Articles

Recommended Articles – August 2017

New entry on our list FPGA4Student is a website dedicated to provide a lot of source code for various FPGA needs. It’s a good resource for learning how to code in Verilog or VHDL. Here is a comparison between Verilog and VHDL: Explain by Examples. Jason Yu from VerilogPro is set to compare implementation of […]

Teo Vasilache

How to Export Functional Coverage from SystemC to SystemVerilog

This post presents a way to collect functional coverage from SystemC models using SystemVerilog covergroups and UVM-ML/UVM-Connect. Functional coverage is not standardized yet in SystemC, but there is a workaround for the case of mixed-language(SystemC/SystemVerilog) verification environments. This workaround makes use of covergroups from SystemVerilog and TLM transactions from SystemC and SystemVerilog. When a sampling […]

AMIQ Education Program

Open Source Summer School Labs

The last Digital Circuits Simulation and Verification summer school made me wonder: why restrict access to the labs to only those students that can join the summer course? why not give access to the labs to any student that wished to take the course but couldn’t join due to various reasons? That is why I […]

AMIQ Education Program

Amiq Education Program Updates Summer 2017

I just came back from vacation and my fingers are restless, urging me to share with you some of the Amiq Education Program’s latest activities. First Generation of Students to Graduate under the Guidance of the AMIQ Education Program It’s celebration time: three students mentored under the AMIQ Education Program graduated at the beginning of […]

Recommended Articles

Recommended Articles – July 2017

 Tudor (Verification Gentleman) continues his series of articles on unit testing with a case study on Testing SVA Properties and Sequences.  Ben Cohen (SystemVerilog.us) goes into details on how tasks and threads are used inside System Verilog Assertions. The Understanding the SVA Engine + Simple alternate solutions article also includes an SVA example that is […]