Recommended Articles

Recommended Articles – October 2018

Cristian from CFSVision wrote a short tutorial on how to work with SystemVerilog queues. Cadence published a new article in the series regarding SystemVerilog code optimizations. This time it tackles the subject of creating and managing dynamic objects. AnySilicon published an article aiming to describe the stages of ASIC production. The big picture always helps […]

Recommended Articles

Recommended Articles – September 2018

In case of e-language it is the aspect oriented-nature of the language itself that helps cutting down the compile and simulation rerun time. You can read more about dynamic load or just-in-time patching: Adding a Patch Just in Time!. I always try to find ways of shortening the time it takes to wait for various […]

Recommended Articles

Recommended Articles – August 2018

In his article about how to avoid FIFO overflows, Stefan promised a second solution. Here is part II of the article presenting the solution which makes use of uvm constructs. Neil from AgileSOC continues to simplify the SVAUnit framework. He makes use of his new mocking framework in order to decouple the driver from the […]

Stefan Birman

How To Protect FIFOs Against Overflow – Part 2

This post is a follow-up of the How To Protect FIFOs Against Overflow – Part 1 and it details the second proposed solution. The complete implementation presented in this post can be downloaded from GitHub. That being said, let’s go through the implementation, step-by-step. Step 1. Define enumeration items that identify the two FIFOs typedef […]

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Recommended Articles – July 2018

AMIQ Education Program saga continues…. This years’ summer school received more attention from the students according to Stefan’s feedback: Digital Circuits Simulation and Verification Summer School. FIFOs are encountered in many digital designs and the verification of such designs comes with specific challenges, one of them being to protect the FIFOs against overflow. You can […]

Stefan Birman

How To Protect FIFOs Against Overflow – Part 1

Systems containing FIFOs face verification engineers with a “classic” black-box verification problem: how to protect FIFOs against overflow in order to avoid unpredictable loss of packets. The difficulty in solving this problem comes from the lack of visibility into DUT’s internal states, which means the solution should count only on the events/packets driven/monitored on the […]