Recommended Articles

Recommended Articles – January 2019

New entry on our list. Recently, I found a new source of interesting papers related to UVM and Verification. It is the Rochester Institute of Technology (RIT) Scholar Works. RIT is a tech University from New-York, USA. Of particular interest are the theses papers published on their website. Here are some papers which tackle various […]

Aurelian Ionel Munteanu

How to Call C-functions from SystemVerilog Using DPI-C

Recently I played a bit with SystemVerilog and DPI-C and I thought of sharing the experience with you. This post shows data types mappings from SystemVerilog to C and how to call C-functions from SV. I also provide a simple SV/C application to facilitate understanding of data types mappings. Data Mappings When SystemVerilog interacts with […]

Recommended Articles

Recommended Articles – December 2018

Sergiu Duda from AMIQ has put a lot of effort into creating a high quality article on the non-trivial topics of High Level Synthesis and Deep Learning. The later, is not found in the everyday terminology of a verification engineer. Deep learning is just a flavour of a bigger part called Machine Learning which in […]

Sergiu Duda

How to Implement a Convolutional Neural Network Using High Level Synthesis

Introduction Deep Learning has taken the world by storm and now has applications in almost every field, from image and speech recognition to medical software, from data analysis to the fine arts. Even though the idea of Deep Learning is not new and the basic principle is pretty straightforward, only recently has it grown in […]

Recommended Articles

Recommended Articles – November 2018

New data arrived from the 2018 Wilson Research Group Functional Verification Study. This research is done every two years and it shows trends in our functional verification domain. If you are interested in the data you can read the set of articles that will follow on verification horizons. Here are the first ones: Prologue, Part […]

Stefan Birman

Highlights of DVCon EU 2018

This post presents some of the highlights of the technical program AMIQ consultants enjoyed attending at DVCon Europe 2018 (24-25 October, Munich).   Hot Topics It is quite hard choosing a “hottest” topic, but we did notice that PSS- and SystemC-related papers/tutorials engaged a lot of engineers in discussions.   SystemC, Virtual Platforms, System Modeling […]