Horia-Răzvan Enescu

How to Avoid Parameter Creep for Parameterizable Agents and Interfaces

For configurable protocols, it is useful to have a single agent which can adapt to any protocol configuration. If the agent and the interface are parameterized, having a large number of configuration options will require using many parameters. This can quickly lead to parameter creep: explicitly specifying and propagating all the parameters throughout the environment. […]

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Recommended Articles – October 2017

Cristian from CFSVision continues the SystemC series with two new tutorials addressing Time, Events and Processes and Mutex, Semaphores and FIFOs. Stefan from Amiq shows how to create a custom sequencer arbitration policy in UVM. In AMIQ Resources page you can find the contents of AMIQ’s bookshelf, papers and the list of blogs we periodically […]

Stefan Birman

How To Customize UVM Sequencer’s Arbitration Policy

This post shows how you can implement a custom sequencer arbitration policy in UVM. The example considers a sequence that contains a field called seq_type: typedef enum {MASTER_SEQ, REQ_SEQ, CNFRM_SEQ, ACK_SEQ, REDO_SEQ, DATA_SEQ } ex_seq_type_t; class ex_base_sequence extends uvm_sequence#(ex_sequence_item); ex_seq_type_t seq_type; // this field is used by the arbitration scheme …….. endclass The arbitration policy […]

Stefan Birman

Highlights of ORConf 2017

During September 8-10, 2017, I attended the ORConf conference, which is part of the Wuthering Bytes Festival of Technology. The conference is run by the Free and Open Source Silicon Foundation. There were about 60 participants in total, all with different backgrounds: academia, hobbyists, FPGA-based design, law, software development, embedded system design and business. The […]

Recommended Articles

Recommended Articles – September 2017

CFSVision continues the SystemC tutorial with an indepth explanation of the sc_module: Learning SystemC: #002 Module – sc_module FPGA4Student explains how to implement a car parking system in VHDL. Working both with SystemC and SystemVerilog is not always an easy task. Teo from AMIQ facilitates understanding of data structures mirroring between SystemVerilog and SystemC: How […]

Teo Vasilache

How to Align SystemVerilog-to-SystemC TLM Transactions Definitions

This post presents a method to align definitions of the objects defined in SystemVerilog and SystemC. An object from SystemVerilog is aligned with an object in SystemC if they both have the same fields with same data types. Verification projects that use both SystemVerilog and SystemC make use of TLM transactions to exchange data between […]