Marius Cătălin Gherasim

Register Agent: A UVC for Register Access

The register verification process consists of access verification and functional verification. Register access verification ensures that each register can be correctly accessed in any succession of transactions, with no DUT (Design Under Test) freezing, etc. In order to achieve this, a large spectrum of transactions needs to be generated with high reaccess frequencies for the […]

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Recommended Articles – September 2020

Did you know that you can match strings using regular expressions from within SystemVerilog code? UVM implements a function called uvm_re_match. My colleague, Florin Oancea, explains how to use it and what you should pay attention at: How to Match Strings in SystemVerilog Using Regular Expressions In the August edition of the recommended articles I […]

Florin Oancea

How to Match Strings in SystemVerilog Using Regular Expressions

Recently, I needed to filter out some instance paths from my UVM testbench hierarchy. I discovered that this can be done using regular expressions and that UVM already has a function called uvm_pkg::uvm_re_match(), which is a DPI-C function that makes use of the POSIX function regexec() to perform a string match. The uvm_re_match function will […]

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Recommended Articles – August 2020

Ioana Cristea from Amiq shows how to achieve a non blocking communication between the SystemVerilog simulator and an external component, like Python: Non-Blocking Socket Communication in SystemVerilog Using DPI-C. Neil Johnson and Dave Rich have launched a challenge to the verification community. Discover and fix race conditions inside 10 SystemVerilog code snippets. Read more in […]

Ioana Catalina Cristea

Non-Blocking Socket Communication in SystemVerilog Using DPI-C

As discussed in a previous article (How to Connect SystemVerilog with Python), functional verification may require an interaction between the testbench and components written in various programming languages. The above-mentioned post describes a method for connecting SystemVerilog with Python that assumes a one-to-one relationship between the sent and received packets. This implies that the communication […]

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Recommended Articles – July 2020

Neil Johnson announced he will take a step back and pass the leadership of SVUnit project to Tudor Timisescu, aka Verification Gentleman. SVUnit is a consistent and valuable contribution to the verification community and I am happy it is not lost. That’s the OpenSource spirit at work! Welcome back Manish! After four years of silence, […]