Last year, Tudor Timisescu from the Verification Gentleman published an article about Formal Verification. More exact it is A Comparison of Formal and Simulation for a Simple, Yet Non-Trivial Design – Part 1. In this part 1 he describes an imaginary design and builds assertions and properties out of it, for the scope of using formal verification concepts.
Even if the following is a presentation from 2019 DVCon conference, it is still valuable for people using UVM. Cliff Cummings, has a great experience with SystemVerilog and UVM. He is one of the people who worked on the Verilog and SystemVerilog standards. In these 2 videos posted on the Accellera website, he presents in a simple yet comprehensive way, how certain UVM mechanisms (e.g. messaging, transactions, sequences, analysis ports) are working or are intended to work. I highly recommend you view both presentations: Gain Valuable Insight into — and Make the Most Out of — the Changes and Features that Are Part of the New IEEE 1800.2 Standard for UVM
Last year, Chris Spear and Rich Edelman, wrote several UVM coding guidelines on how to offer clarity in a complex world.
Yoav from Foretellix, continues his quest to understand and define ADAS (Advanced Driver-Assistance Systems) and AV (Autonomous Vehicle) related topics. This time he is looking on how to estimate the residual risk of ADAS / AV: part1 and part2