AMIQ has released a new UVC that facilitates register accesses. It is called Register Agent: Register Agent: A UVC for Register Access.
Manish from Learn UVM Verification explains why we need a UVM Register Abstraction Layer: Why UVM RAL is needed?.
Cadence released a new feature that allows you to integrate Python code into e-language. They now provide a nice example for visualizing the vr_ad register accesses in the form of a heatmap. The Python code is OpenSource and you may use it in your e-Language project: Ouch that’s Hot! Register Access Heatmap.
In AMIQ Resources page you can find the contents of AMIQ’s bookshelf, papers and the list of blogs we periodically scan for recommended articles.
Enjoy!
SystemVerilog and SVA Cheatsheet