In early 2018, AMIQ released a new library called FC4SC (Functional Coverage for SystemC). The community responded in a positive manner and started to evaluate it and asked for improvements. Late this year, the library has been donated to Accellera in order to fill the functional coverage gap from the SystemC world. More on the reasoning behind the library and its future in this article: AMIQ Consulting Contributes C++ Coverage Library to Accellera
Adam Rose, from Verilab, wrote a paper in the form of enhancement proposals for the SystemVerilog language standard. He looked at Python and C++ and tried to borough concepts and apply them to SystemVerilog. In this new SystemVerilog language quest (anonymous classes, introspection, decoration), he described how code constructs like uvm_macros, uvm_factory, constraints and functions would morph into a different kind of code constructs and not only. I think the final paragraph summarizes the goal of the paper:
In many ways, these enhancements simply bring SystemVerilog up to date with recent
developments in programming languages. By using them, Verification engineers will be able
to enhance their productivity by writing more concise, modular and maintainable code.
This is the last article for 2019, thus, I take the chance to wish you a Merry Christmas and hope, we all contribute to a better, safer and peaceful new year. Happy New 2020!
Enjoy the holidays!