New entry on our list. Recently, I found a new source of interesting papers related to UVM and Verification. It is the Rochester Institute of Technology (RIT) Scholar Works. RIT is a tech University from New-York, USA. Of particular interest are the theses papers published on their website. Here are some papers which tackle various topics:
- Design and Verification of a Round-Robin Arbiter – by Aung Toe
- UVM Verification of an SPI Master Core – by Deepak Siddharth Parthipan
- Configurable Random Instruction Generator for RISC Processors – by Krunal Mange
- Reconfigurable Model for RISC Processors – by Thiago Pinheiro Felix da Silva e Lima
Interfacing SystemVerilog with C language is a common thing nowadays. Mapping the data types between the two languages might become troublesome, thus the need for this article: How to Call C-functions from SystemVerilog Using DPI-C
Dave Rich, is one of the industry experts in SystemVerilog and UVM. He started a series of posts which may help newbies and experts alike in absorbing knowledge required by the verification activity. In one of the articles, he talks about SystemVerilog classes for UVM verification and in a second article he’s presenting some of the usual design patterns in SystemVerilog OOP.
Portable Stimulus can be used to create better virtual sequences. This is the story which Matthew Ballance presents in this article from Verification Academy.
Yoav Hollander, the creator of e-language, is leading the way in getting safer AVs (autonomous vehicles). It is a brand new territory where innovation and challenges are day to day activities. In his last January post, he’s challenging the idea that Monte Carlo simulations (which use the expected distribution) are safe to use in AV verification.