It is quite hard choosing a “hottest” topic, but we did notice that PSS- and SystemC-related papers/tutorials engaged a lot of engineers in discussions.
SystemC, Virtual Platforms, System Modeling
The SystemC Evolution Day workshop took place on 23 October, one day before DVCon. The room was full and there were definitely more participants than in 2017. System modeling is gaining increasing traction as the complexity of systems increases, so it is only natural to see more engineers interested in system modeling with SystemC.
The first “panel” that comes to my mind is the one about SystemC Multi-language Requirements. The field of verification is expanding, crossing borders between technologies, which in turn calls for standardized ways to make different technologies (e.g. verification and modeling languages) work together. This is why Accellera created the Multi-Language Verification Working Group. One of the group’s goals is to introduce “the Universal Verification Methodology (UVM) concepts in other sophisticated environments and languages”. There is already an ongoing effort to implement a SystemC UVM library.
Dragos Dospinescu (AMIQ Consulting) presented the Functional Coverage for SystemC (FC4SC) library. There was a lot of interest among participants in this since functional coverage is a missing piece in the SystemC verification library puzzle. Dragoș received a lot of feedback and feature requests, which gives him the energy to continue supporting this library. You can take a look at the FC4SC GitHub repo if you want to delve into the small details or simply try it out for yourself.
Overall, I recommend you attend this forum if you want to keep up to date with the latest trends and discussions around SystemC.
The Portable Test and Stimulus Standard continues its ascending trend from previous years. PSS is a new standard/technology and engineers are still learning about it, which explains why most presentations are given by the creators of PSS themselves (e.g. the members of the Accellera PSS Working Group). As soon as it starts to be adopted, we should see more papers resulting from real life projects.
We found Tutorial 5 – Accellera Portable Test and Stimulus: The Next Level of Verification Productivity is Here (given by Tom Fitzpatrick from Mentor and Sharon Rosenberg of Cadence Design Systems) to be very instructive as to what PSS is and what we should use it for. The presentation was crisp and to the point, providing relevant examples and analogies. The presenters went through various PSS concepts, such as components, resources, bindings, coverage, inference mechanisms and scenario generation. What I found of great importance, and something the tutorial highlighted very well, was that using PSS requires a new mindset compared to traditional unit-testing or SystemVerilog/UVM functional verification.
Andrei Vintila (AMIQ Consulting) presented the Portable Stimulus Driven SystemVerilog/UVM Verification Environment for the Verification of a High-capacity Ethernet Communication Endpoint. Andrei identified the possibility of replacing top level UVM sequences with PSS actions/scenarios and explained how to leverage the power of PSS in practice. The stimuli model he presented enables horizontal reuse across projects and vertical reuse from block level up to top level verification, as well as provideing multiple test variations.
The third presentation we enjoyed was 6.3 MicroTESK: Automated Architecture Validation Suite Generator for Microprocessors, presented by Alexander Kamkin (Ivannikov Institute for System Programming of the RAS). Alexander presented the MicroTESK microprocessor test program generator, which can be adapted to different ISA architectures. MicroTESK is capable of generating random, legal, and self-checking test programs by leveraging various algorithms, tools (e.g. the Z3 constraint solver), and languages (e.g. Ruby, Sim-nML).
SystemVerilog and UVM
Well, well…it seems there is still some “juice” left in SystemVerilog and UVM.
The first highlight was the tutorial by Mark Litterick (Verilab) UVM Audit: Assessing UVM Testbenches to Expose Coding Errors and Improve Quality. Mark presented a strategy and guidelines for auditing UVM code. He also provided a comprehensive list of “sensitive points” to look out for when assessing the quality and level of reusability.
The second highlight was Sarmad Dahir’s (Cadence Design Systems) presentation on UVM-ML,Using UVM-ML Library to Enable Reuse of TLM2.0 Models in UVM Test Benches. The UVM-ML library provides support for SystemVerilog/UVM and SystemC environment interoperability by using TLM and DPI mechanisms. Sarmad provided a step-by-step guide to how SystemC structures should be implemented for different implementation requirements. It was a real tutorial from this point of view. As a side comment: there is no general consensus (yet) regarding multi-language support, given that Mentor provides a similar library called UVM-Connect. Maybe the Accellera Multi-language Working Group will address this.
Darko Tomusilovic (VTool) presented Extending functionality of UVM components by using Visitor design pattern. The presentation introduced the visitor software pattern and showed how it can be used to extend the UVM messaging system.
Tutorial 8 – Firmware Firmly under Control: New Optimization and Verification Techniques for Application Specific Electronic Systems included two interesting presentations.
The first presentation was T2. Design-Time Optimization Techniques for Low-Power Embedded Memory Subsystems, presented by Manuel Strobel (University of Stuttgart). Manuel provided insights on different SRAM memory optimization practices. Taking into account both static and dynamic power consumption, he described various potential techniques, ranging from addressing the issue at the software level down to the design level. Experiment results were also showed to have reduced overall energy consumption by up to 80% in some cases.
The second presentation was T5. Properties-First Design: A New Design Methodology for SoC Hardware and Low-Level Software, presented by Tobias Ludwig (TU Kaiserslautern). Tobias described a way to mediate the discrepancies between system-level models and RTL implementations by establishing a firm relationship between the two. This relationship manifests itself through the abstraction of each low-level (RTL) feature into a graph for which certain properties are checked. If the properties hold, then the verification results obtained at system level translate to RTL, without the need to verify the same behavior at the block level.
Functional Safety Verification (ISO-26262)
Ann Keffer (Cadence Design Systems) presented one of the most popular technical tutorials: Tutorial 11 – Making ISO26262 Functional Safety Verification a Natural Extension of Functional Verification. The tutorial first introduced ISO26262 and functional safety verification concepts. It then moved onto the similarities and differences between functional verification and functional safety verification, along with the methodology required to align the two. Ann was able to demonstrate the natural connection between functional verification and functional safety verification.
AI, Machine Learning, Deep Learning
There were also a number of presentations that included AI&related technologies in their titles or descriptions, something we will probably see more of at future conferences.
Tutorial 4 – Machine Learning Introduction and Exemplary Application in Embedded Wireless Platforms, by Jonathan Ah Sue (Intel Germany), showed how Intel used machine learning techniques to optimize the power consumption of an Intel modem (the “Cognitive Power Controller” project). Given that machine learning was not a target topic of the conference, the speaker began by giving a comprehensive introduction. Unfortunately the allocated time slot was not sufficient to allow him to delve into the implementation details.
The Best Paper Award, sponsored by AMIQ, went to Thilo Vörtler, Karsten Einwich (COSEDA Technologies), Muhammad Hassan (DFKI) and Daniel Grosse (University of Bremen & DFKI) for the paper 12.1: Using Constraints for SystemC AMS Design and Verification.
AMIQ is a traditional sponsor of DVCon and was again present with an exhibition stand. We had lots of visitors this year and held many interesting discussions on EDA topics and verification. We definitely had more visitors this year compared with 2017.
Many thanks to this year’s organizers and the Technical Program Committee for the, as always, excellent service and content.
I would also like to thank the AMIQ engineers for their contributions to this post.
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