The course setup was similar with the 2017 one: 8 hours a day for 5 days, same place, same device under test, similar introduction into verification theory. Students used Cadence’s Incisive Simulator for SystemVerilog/UVM exercises (licenses provided through Europractice). Students used DVT for code editing and syntax support (e.g. autocomplete, syntax suggestions, hyperlinks, macro expansion).
Compared with 2017 edition:
- I further reduced the amount of theoretical concepts to ~5 hours
- the exercise was solved by teams of 2 students: more fun, faster progress
- exercise used a UVM verification environment template where they were requested to fill in certain functions/tasks and build an agent from scratch
The 2018 participants required less time to refresh their knowledge of Verilog constructs and digital circuits simulation concepts. Given the exercise was based on a UVM verification environment template the progress was a bit slow at the beginning, still they pushed forward and by the third day they were up to speed. What I appreciate the most is that ALL students were eager to complete the course and they were not put off by the intensive schedule or by ramp-up effort.
The main goal of the summer school is to provide a glimpse into the world of verification: what kind of knowledge is required, how to define and implement a verification project, what are the kind of tasks that must be solved. In that sense I think this year’s edition provided a better experience thanks to the feedback received from previous editions’ participants.
Similar to previous editions, at the end of the course each student received a Certificate of Participation.