Here is an interesting article discussing if any FPGA implementation contains an internal tri-state bus or not: FPGA internal tri-state buses
I’m not a fan of long articles, but the subject of the following ones is of real interest for verification engineers. It is a transcript of a discussion between representatives of major EDA companies about EDA tools and their option of going to the cloud. Tools and the future of those tools might influence how we do verification in the future. You can read their discussion in a series of three articles from Brian Bailey-SemiEngineering: EDA in the cloud Part1, Part2, Part3.
Every experienced verification engineer has been at least once through the scenario described by Mark Glasser in his last article: Debugging madness. The way we can deal with these kind of “brain stalls” is diverse. It might also help if we understand how the brain works and how learning process works. I strongly suggest to follow up a course about “Learning How to Learn” from Coursera.
Neil Johnson steps out of the verification circle and uses his critical thinking to address the high level picture about Verification. He also tries to connect the dots through the lens of his past experiences in verification. Verification Planning with shared objectives is considered, followed by metrics for design maturity and then finding a cure for what he calls “coverage hangover“