Recommended Articles – January 2018

Recommended Articles

Jason, from VerilogPro, dives into the details of generate constructs from verilog and how they can be used to build a configurable RTL: Verilog Generate, Configurable RTL Designs

Horia has come with some alternative implementations for bitwise coverage in SystemVerilog. Here you can see his implementations: How To: Alternative ways to implement bitwise coverage

Cadence has shared some nice macro code for its Specman users. The macros are helpful when dealing with coverage (minimum and maximum of a type). Read the full details

In AMIQ Resources page you can find the contents of AMIQ’s bookshelf, papers and the list of blogs we periodically scan for recommended articles.



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