There were about 60 participants in total, all with different backgrounds: academia, hobbyists, FPGA-based design, law, software development, embedded system design and business. The presentations reflected these different backgrounds, as you can see from the schedule.
Note: all references to people and tools/IPs should be understood as being part of or developed by the Open Source community under Open Source licenses.
RISC-V is a hot topic these days, especially now that SiFive and the RISC-V Foundation are behind it. SiFive is a Red Hat kind of business: it provides commercial support for RISC-V based IPs (see more here). The RISC-V Foundation has an impressive list of members and it takes care of RISC-V ISA development, maintenance and adoption (see more here).
I would like to mention the following for their professional and high quality presentations:
- Alex Bradbury from lowRISC, who provided an overview of recent RISC-V Foundation activities and the lowRISC project status (the SW stack for RISC-V)
- Graham Markall, who described his experience of deploying cycle-accurate models of RISC-V cores
- Davide Rossi of the University of Bologna, who presented PULP: an Open Source Parallel Computing Platform, an IP that was already taped out at the beginning of 2017
SiFive+RISC-V Foundation ecosystem is the new, strong and determined ARM competitor in town.
A number of tools were presented and I had the chance to meet some of the engineers behind the Open Source EDA, such as:
- Esko Pekkarinen, PhD at Tampere University of Technology, who presented Kactus2, an IP-XACT Register management tool
- Timothy Edwards, of Open Circuit Design, who presented the EDA SW stack he maintains and described the problems encountered during development. His dedication to the project is impressive.
- Clifford Wolf, who is behind the Yosys synthesis tool, the SymbiYosys formal engine and the PicoRV32
- Dan Gisselquist, the creator of www.zipcpu.com, who presented the AutoFPGA, a bus topology generation tool
Clifford Wolf presented a formal proof kit for RISC-V based on his Open Source formal engine.
Tobias Strauch presented “The free and open Programming, Design and Verification Language (PDVL)” he is currently developing. There is still a long way to go to make it usable for practical projects. Unfortunately, I was unable to find any sources or documentation on PDVL and it is not clear when he is going make the language available to the public.
LibreCores has two goals: 1) to be a focal point for IPs, and 2) to increase industry’s trust in IPs. The LibreCores project is a gateway to projects hosted on other servers (e.g. GitHub, BitBucket etc., even OpenCores) and provides basic project statistics (e.g. number of downloads, voting, versioning system activity, etc.).
Open Source License Alternatives
Andrew Katz presented various aspects of Open Source licensing with a focus on CERN OHL v2 and copyleft licenses for RTL IPs.
Open Source HW is an invitation to mix business and pleasure…..and I’m not the only one to see it as such! How profitable will they be? Only time will tell.
Chips4Makers is a business initiative of Staf Verhaegen that aims to help ASIC/FPGA enthusiasts produce ASICs in very low volumes by simplifying the paperwork involved and providing factory alternatives and sustainable pricing. Staf intends to set up a crowdsourcing campaign so as to be ready to begin providing services by September 2018. While an interesting idea, I wonder how big the market will be for these ASICs?
VLSI System Design, introduced by co-founder Kunal Ghosh, is a company that has created a set of tutorials on EDA tools. These tutorials demonstrate how to use EDA tools with the help of EDA alternatives.
There were few “…Update” presentations describing the progress made on various projects. Although not among the most interesting presentations at the conference, they showed how people were still working on their projects.
The City, the Venue, the People
The conference was hosted at The Waterfront Hall belonging to the Town Hall in Hebden Bridge, Yorkshire, UK. The long journey from Bucharest was soon forgotten once we reached this beautiful town with its beautiful scenery, architecture and natural surroundings. The rainy weather with magnificent intermittent sunbursts together with interesting discussions, proper ale and pies kept the spirits high.
I would like to thank the conference hosts for their warm welcome and for giving their Saturday and Sunday to the Open Source community.
My Very Personal Conclusions
ORConf is a great conference to attend if you are into Open Source, academia, making stuff for the fun of it, or just passionate about technology. There you will get the chance to meet people that make HW/SW stuff at home and give it away for others to use. It also provides career and networking opportunities.
While overall my experience of the conference was good, it still left me with some mixed feelings. I will try to explain.
On one hand, I could see they have the passion and energy to make things work. On the other, I could see the challenges they need to overcome in order to make IPs more attractive for the industry.
The first challenge has to do with the nature of HW: the path from design to implementation is much longer and more costly compared with the equivalent path for SW. A HW bug can kill the product and/or have devastating effects on the company, which is why companies are reluctant to use IPs. Will the community be able to provide quality metrics (e.g. verification metrics, self-checking test suites, coding style, synthesis results and verification documentation) or proof that it works in a real life project already (i.e. silicon proven)?
Another challenge has to do with the size of the community: it is very, very small compared with an SW counterpart. This post analyzes in detail about the importance of the community’s size. Will they be able to grow in size? Will they be able to increase their collaboration with academia in order to get more “hands on deck”?
I noticed the diversity of voices and projects, which is a good thing and a desirable state of affairs. But this only gave rise to other questions: Will they be able to work together, as a team, on common projects? Will they be able to reduce fragmentation?
The FOSSi Foundation has put a lot of effort into new projects like LibreCores, FUSESoc, IPs, etc. Reuse is probably the King and Queen of Open Source efficiency sources, but still they seem to shy away from OpenCores. Why? Have they assessed the quality and reusability of the OpenCores IPs? Will they make the effort to reuse some of those projects?
LibreCores has the potential to bring the community closer together and, more importantly, it can increase confidence by implementing quality indicators. Will they be able to add quality indicators, such as: presence of self-checking tests, status of the last regression, verification metrics (code coverage, assertion coverage, etc.), FPGA or ASIC implementation status (e.g. FPGA synthesis reports), host interface protocol compatibility (e.g. AXI, WBI, etc.), compatibility with other IPs (i.e. a master/slave-type relationship), documentation status, FuseSoC compatibility, CI ready, issue statistics, etc.?
Next round’s on me!! Cheers!
PS: You can see more pictures on AMIQ Consulting’s Facebook page.