First Generation of Students to Graduate under the Guidance of the AMIQ Education Program
Timeline and Setup
The students worked part-time on their projects, except during vacations (i.e. holidays, exam sessions, etc.). In total they did the equivalent of about 3 months of full time work. Most of the work was done at AMIQ premises under supervision from AMIQ engineers. The students communicated the project status and DUT issues to the designer or supervisor periodically or as required by the project.
The verification environments were implemented in SystemVerilog/UVM/UVM-ML. The simulations were run using Cadence’s Incisive Simulator and Incisive vManager. The project deliverables (sources, documentation etc.) were uploaded to the DCAE department’s Git repository.
I will now give the stage to the DCAE staff and students to share their view of the project.
In the DCAE lab we developed as a research project a hardware accelerator for L1/L2 norms with applications in visual search (see article). The RTL implementation was smoke tested using an FPGA implementation and a suite of C++ tests running on a C++ model, but we felt there was a need for more verification in order to ensure that scalability, latency and throughput were as desired.
I decided to delegate the verification task to students working under the supervision of AMIQ engineers. I played the role of designer: answering their questions, fixing bugs, changing the implementation if required, and updating the specifications, etc. It was fun and the students managed to uncover some important implementation issues. I am proud of their having achieved good grades (10/10, 9.8/10 and 9/10, respectively) on their graduation theses and I wish them the best of luck with their future ventures!
This approach based around student graduation theses is definitely a win-win-win situation for students, university, and industry.
Lucian Petrica, Assistant Professor at the Department of Electronic Devices, Circuits and Architectures, FET, Politehnica University of Bucharest
My task was to verify the I/O controller. This was my first functional verification project and I was happy to discover that functional verification provides a nice mix of object-oriented programming and hardware design. I found a number of bugs, some of them critical, and I managed to accomplish the verification goals that I defined during the verification planning phase. Another part that I enjoyed was the design and implementation of a VIP that was then reused by Dragos.
I think this project was a good way to obtain first-hand experience with functional verification and the requirements of a real-life project.
Madalina Gheboianu, Graduate of Technologies and Telecommunication Systems, FET, Politehnica University of Bucharest
I was in charge of the verification of the processor controller. Although I’ve done functional verification training before and I have practical experience of SystemVerilog/UVM, this was my first beginning-to-end verification project based on a real-life DUT. It was an interesting project that allowed me to dive deeper into the functional verification process.
Another interesting experience within the project was my acting as scrum master for the team, allowing me to put into practice the Agile methodology knowledge I already had.
Andrei Vintila, Graduate of Computers and Information Technology, FET, Politehnica University of Bucharest
I verified the ALU core that supported 35 arithmetic and logic instructions. Given my extensive experience with OOP, the coding of the VE was straightforward. The interesting parts involved generating valid programs and modelling the DUT using SystemC. I found the blend of SystemVerilog, SystemC and UVM-ML very appealing.
Unfortunately, the available time didn’t allow for a 100% completion of the verification goals, but I am confident it will be easy for someone else to take over the VE and continue my work.
Dragos Dospinescu, Graduate of Computer Systems Architecture, Faculty of Computers and Automation, Politehnica University of Bucharest
You can see few photos taken during thesis presentations on AMIQ Facebook page.
About the AMIQ Education Program – Graduate Thesis
Digital Circuits Simulation and Verification Summer School
There were, however, a few changes from the 2016 edition:
- The course was delivered in a different lab (A414) with different IT infrastructure, but the IT admin did a wonderful job and everything worked seamlessly.
- The course structure was changed to 8 hours a day for 1 week, which proved to be more efficient timewise both for myself and for the students.
- The students used ModelSim-Altera Edition for basic Verilog and digital simulation exercises and the Cadence’s Incisive Simulator for more advanced SystemVerilog exercises (licenses provided through Europractice).
- There was a completely new DUT specification with RTL sources containing real bugs.
I still allocated approximately 7 hours to the theoretical concepts, the Verification Engineer job description and other technical- and career path-related issues.
Every group of students is different and brings with it its own background and energy. Compared with those in 2016, the 2017 participants needed more time to refresh their knowledge of Verilog constructs and digital circuit simulation concepts, and this prevented me from discussing any UVM topics. It also took the students comparatively longer to understand the SystemVerilog language constructs and basic verification environment architecture. This is understandable given that they had had less practical OOP experience. On the other hand, they were more dedicated and committed to completing the labs.