Using SystemVerilog along UVM methodology can be a difficult road for a newbie. Mentor together with Sandeep Nasa and Shankar Arora from Logic Fruit Technologies, have compiled a list of UVM tips&tricks that help you avoid some of the language traps and might improve performance. Read more on UVM Tips and Tricks
Cadence has added static members in the e-language, so from now on you can share configuration, coverage or fields among all instances of a struct/unit. Take a look at this new feature in Static members in e
Communication within an UVM environment is mainly done using ports (analysis, TLM, etc.). A complex hierarchy of port connections slows down the debug…well, not for Munjal which describes a way to speed-up the debug: How to find UVM port connections between components in the testbench.
This year DVCon US enchanted us with few innovative approaches on verification challenges. See more in AMIQ’s Highlights of DVCon US 2017.
You take a 3rd year student, a mentor and an idea and stir (not shake) them. Read about the result on AMIQ’s blog: Mentoring Young Talent Through Hands-on Applications. This is part of the AMIQ Education Program.