Well, well. The Summer Course saga continues…
Between 27th of June and 8th of July I delivered the Digital Circuits Simulation and Verification Course organized by the Department of Electronic Devices, Circuits and Architectures, within Politehnica University of Bucharest. This course was an improved version of the 2015’s Summer School.
This year I was better prepared given the experience of the last summer’s course. We launched the poster and the official announcement on 15th of May, which gave students plenty of time to apply. This doubled the number of applications and a further selection was required. Most of the applicants were 2nd year graduates. Beside students, the course was also attended by Marius Enachescu, Teaching Assistant, and Mariana Ilas, Assistant Professor. They wanted to get in touch with the verification domain and get a fresh view of the industry’s requirements for the electronics graduates that want to pursue a verification career path.
The structure of the course was: 2 weeks, 4 hours a day, consisting of 8 hours of theory and the rest being allocated for hands-on exercises. The exercises were focused on basic verification components and metrics using SystemVerilog and UVM.
I integrated last summer’s feedback and I extended a bit the 2015 agenda:
- Light Introduction to Digital Circuits Verification Domain
- Verification Engineer – Job Description Presentation new
- Digital Circuits Simulation new
- Verification Cycle from Specification to Sign-off
- Verification Tools, Languages and Methodologies
- Metric Driven Verification Planning
- The Verification Environment
- Stimulus Generation
- Monitors and Checkers
- Metrics Definition and Collection
- Light introduction in UVM
The extra items I presented this year were requested by 2015 edition’s participants. The Job Description Presentation relates the responsibilities and knowledge of a verification engineer to the courses provided by Faculty of Electronics and Communications.
The topic of Digital Circuits Simulation refreshes some of the basic Verilog constructs and digital circuits simulation concepts. Additionally the labs were adjusted to better match the students’ level of knowledge/experience.
At the end of the course each student received a Certificate of Achievement or a Certificate of Participation, depending on their performance and involvement.
The feedback I received confirmed the changes I made to the course: smoother theory go-through, students solved exercises at a faster pace, more specific questions. Also I noticed a higher involvement of the students: some of them went beyond my expectations and requested trial licenses to Mentor, installed Modelsim™ and continued to work in their spare time.
During the course I received lots of questions about the industry, career build-up and companies’ view on their activity. Some of them plan to follow the “microelectronics” path, others dream of going towards embedded systems, others see themselves as analog designers, but all of them asked basically the same question: what should I do to get there? The discussions showed that students have a lot of energy and motivation that sometimes they don’t know how to channel towards their goals. Although I answered their questions on the spot, it gave me food for thought that I plan to structure in another article.
I would like to thank Assistant Professor Lucian Petrica and IT personnel(Ciprian Motricala, Radu Pirea) for the support and all students for their involvement.
It was a valuable experience on both professional and personal levels and I also got some homework for the 2017 summer course.