Recommended Articles – June 2016

Recommended Articles

Implementing coverage in SystemVerilog can become a challenging task. Horia presents the last article from a series of 3, on how to implement flexible coverage.
AMIQ: How to Implement Flexible Coverage Definitions (Part 3)

Henry Chan presents a high level overview of the uvm_reg package:
SemiEngineering: UVM Register Layer: The Structure

Here it is a funny way of explaining verification to a kid:
Gaurav Jalan: Learning Verification with Angry Birds

You should always use the macro `uvm_error() instead of uvm_report_error() function. Here’s why:
Munjal: Be careful while writing UVM Report Messages

Keisuke Shimizu, from ClueLogic, shows how you can define/redefine the printing policy of UVM objects using do_print and uvm_printer:
ClueLogic: UVM Tutorial for Candy Lovers – 33. Defining do_print

CFSVision highlights a common mistake about naming scopes and constraints in SystemVerilog:
CFSVision: SystemVerilog Gotcha: In-line Constraints Scope

In AMIQ Resources page you can find the contents of AMIQ’s bookshelf, papers, grammar, cheatsheets, recommended articles, and the list of blogs we periodically scan for recommended articles.

Enjoy!


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