Between 14-15th of September I attended the Forum on Specification and Design Languages(FDL) in Barcelona, a niche conference that covers subjects such as modeling languages, system modelling (digital, analog and mixed signal), power and performance modelling, high level synthesis, high performance computing and parallel programming.
There were 2 keynote presentations, 7 lectures and 10 panelists presenting their work-in-progress, 33 papers in total.
The event took place in the Aula Màster of Universitat Politecnica de Catalunya(Campus Nord). The organizers included a visit to the Barcelona Supercomputing Center.
I will go through some of the papers I particularly enjoyed.
Software-level Power Optimization
Dr. David Greaves from Computer Laboratory, University of Cambridge proposes a power measurement API for energy-sensitive System-on-Chip applications (paper Fine-grained Energy/Power Instrumentation for Software-level Efficiency Optimization). Today’s energy profiling tools are quite simplistic and intrusive and do not provide fine-grained energy consumption information (e.g. down to thread/call level), most of them are limited to voltage and total current. Dr Greaves proposes extensions of the gdb-API together with the introduction of a dedicated hardware API. The hardware API consists of a register bank that can trace activity at block level. His work can be found on the spEEDO2 project webpage and an ‘IP’ package is expected to be released soon.
This paper is related to “Whole Systems Energy Transparency”, presented by Dr. Kerstin Eder, University of Bristol, in the Academic Track at CDNLive EMEA 2015. Dr. Kerstin studied the effects of software implementation on power consumption by taking a slightly different path: energy characterization of complete ISA for various architectures which allows energy consumption static analysis. You can find more information on Dr. Kerstin’s project on ENTRA project site; you can read this paper for a quick introduction into energy transparency.
WiSeBat: Accurate Energy Benchmarking of Wireless Sensor Networks
In line with the topics above, Quentin Bramas and Wilfried Dron proposed a SystemC model that accurately benchmarks the power consumption of each network node. Therefore, is able to predict the lifetime of a network (the time until the last node stops). The authors validated the model with measurements made using real network protocols like ContikiMAC, X-MAC and 802.15.4.
Temporal Decoupling of Mixed-Signal SystemC Models
Georg Gläser & Co. gave a presentation ( titled Temporal Decoupling with Error-Bounded Predictive Quantum Control) on a method to speed up mixed signal SystemC models by temporally decoupling digital and analog parts of the model. This paper is based on a model in which the analog part interacts with the digital part quasi-periodically (interaction points fall within a gaussian distribution). His solution is to update the time quanta dynamically (i.e. predictive temporal decoupling), which allows the digital part of the model to be run like any LT/AT TLM model, while the analog part is running cycle-accurate.
Assertion-based code generation
I am interested in both assertion-based verification and code generation, thus I was happy to find two papers which are the perfect blend. The authors consider PSL assertions as a basis for code generation.
Fatemeh Javaheri from Universit´e Grenoble Alpes and CNRS, TIMA Laboratory (paper Revisiting Regular Expressions in SyntHorus2: from PSL SEREs to Hardware) presented SyntHorus2, a tool that can synthesise RTL prototypes (VHDL) out of PSL assertions.
Laurence Pierre from the same laboratory (paper Towards a Toolchain for Assertion-Driven Test Sequence Generation) proposes a way to generate test sequences out of PSL assertions.
Code generation tools work fine as long as the input is correct, which means that assertions should be verified before they are fed into the generator. This highlights even more the necessity of assertion verification, either by assertion verification frameworks like SVAUnit or formal engines (for assertion visualization and exploration).
A Special-Purpose Language for Implementing Pipelined FPGA-based Accelerators
Cristiano Bacelar De Oliveira and Ricardo Menotti presented the current state of LALP, Language for Aggressive Loop Pipelining. LALP is a domain specific, high-level synthesis language that enables fast synthesis of accelerators on FPGAs; LALP focuses on mapping loops to a pipelined computing architecture, while it gives designers full control of each pipeline stage.
I encourage you to participate in FDL: it is rich in content and passionate people and it is very low in “saturated marketing”. I look forward to attend the next FDL which will take place between 14-16’th of September 2016 in Bremen, Germany.
PS: The beauty of the SuperComputing Center is inspiring and it organically compliments Barcelona, the city of Gaudi, Picasso, Dali and Miro.