Although February was a 28 days month the Verification community was more active than on a 31 days month.
The random generation strategy could be the root cause of long time required to achieve coverage closure. Claudia provides a use case scenario for evaluating coverage closure in relation to generation strategy:
AMIQ Blog: A Coverage Closure Study: “on-the-fly” or “top-down” Generation?
Sudoku is fun! Solving it using SystemVerilog constraints multiplies that by 100:
Cluelogic: Hidden Gems of SystemVerilog – 3. Solving Sudoku
Wilson Rearch Group and their Functional Verification study is one-of-a kind study, the conclusions are always interesting and the 2014’s results are no exception. In this first part they bring some insights about the FPGA design:
MentorGraphics, Part 1: The 2014 Wilson Research Group Functional Verification Study
An UVM compliant verification testbench, is a hierarchy of interacting UVM components that are required to work in different configuration settings. Synopsis shows several techniques where uvm_config_db is the key to propagate configuration among all components:
Synopsis: Hierarchal Testbench Configuration Using uvm_config_db
Accellera had initiated a new group that is focusing on a standard for portable stimulus. This is a brand new methodology that could contribute a lot to verification, especially in the “code reuse arena” among different verification levels. It’s worth following the works of this new group:
Accellera: Accellera Systems Initiative Forms Portable Stimulus Working Group
Trent McClements, from Invionics, brings a new insight on SystemVerilog constructs always_latch and always_ff:
Invionics: SystemVerilog Insights: Do always_latch and always_ff provide any real value?
Keisuke Shimizu shows a basic code for connecting “candies” inside SystemVerilog with “candies” inside the C-code. One can raise one’s blood’s sugar level by reading:
ClueLogic: UVM Tutorial for Candy Lovers – 25. Using a C-Model
Bryan Murdock touches a sensitive subject: OpenSource vs EDA. What is the driving force for an Open Source project? Who writes Open Source code? Can Open Source take over the EDA industry? Find out part of the answers in here:
BryanMurdock: Why Open Source Has Not Taken Over EDA
Roman Shenkar explains why we might lose simulation cycles when connecting an event to a full signal bus instead of part of it:
Cadence – TeamSpecman: Don’t Lose Extra Simulation Cycles
Tudor Timisescu challenges the constraint solvers with a well known game, the N-Queens problem:
VerificationGentleman: Fun and Games with CRV: The N-Queens Problem
SystemVerilog might take you by surprise even when you are an experienced user. When you figure out the essence of the surprise, you may name it “a gotcha moment”. Cristian Slav is going to show you a first gotcha in a series of such surprises:
AMIQ Blog: Gotcha: SystemVerilog’s post_randomize() is Called Top-Down Not Bottom-Up